公开(公告)号：US20240120270A1

公开(公告)日：2024-04-11

申请号：US18527618

申请日：2023-12-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West ,  Thomas Dyer Bonifield

IPC: H01L23/522 ,  H01L23/58

CPC classification number: H01L23/5223 ,  H01L23/5227 ,  H01L23/585

Abstract: An integrated circuit includes a semiconductor substrate and a plurality of dielectric layers over the semiconductor substrate, including a top dielectric layer. A metal plate or metal coil is located over the top dielectric layer; a metal ring is located over the top dielectric layer and substantially surrounds the metal plate or metal coil. A protective overcoat overlies the metal ring and overlies the metal plate or metal coil. A trench opening is formed through the protective overcoat, with the trench opening exposing the top dielectric layer between the metal plate/coil and the metal ring, the trench opening substantially surrounding the metal plate or metal coil.

公开(公告)号：US20240113094A1

公开(公告)日：2024-04-04

申请号：US17957847

申请日：2022-09-30

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Sreeram N. S. ,  Kashyap Barot ,  Thomas Dyer Bonifield ,  Byron Lovell Williams ,  Elizabeth Costner Stewart

IPC: H01L25/18 ,  H01F27/28 ,  H01F27/29 ,  H01F27/32 ,  H01L23/00 ,  H01L27/01

CPC classification number: H01L25/18 ,  H01F27/2804 ,  H01F27/29 ,  H01F27/323 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/01 ,  H01F2027/2809 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/06155 ,  H01L2224/0616 ,  H01L2224/4809 ,  H01L2224/48137 ,  H01L2224/48175 ,  H01L2224/4909

Abstract: A microelectronic device includes a galvanic isolation device on a silicon substrate and a semiconductor device on a semiconductor substrate. The galvanic isolation device includes a lower isolation element over the silicon substrate and an upper isolation element above the lower isolation element, separated by a dielectric plateau that comprises inorganic dielectric material extending from the lower isolation element to the upper isolation element. The galvanic isolation device includes lower bond pads connected to the lower isolation element adjacent to the dielectric plateau, and upper bond pads over the dielectric plateau, connected to the upper isolation element. The semiconductor device includes an active component, and device bond pads coupled to the active component. The microelectronic device includes first electrical connections to the lower bond pads and second electrical connections to the upper bond pads. The first electrical connections or the second electrical connections are connected to the device bond pads.

公开(公告)号：US20230369198A1

公开(公告)日：2023-11-16

申请号：US17936316

申请日：2022-09-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Elizabeth Stewart ,  Jeffrey Alan West ,  Byron Williams ,  Pijush Kanti Ghosh

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L21/76832 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/48101 ,  H01L2224/48138 ,  H01L2924/1205

Abstract: The present disclosure generally relates to a capacitor on an integrated circuit (IC) die. In an example, a package includes first and second IC dice. The first IC die includes a first circuit, a capacitor, and a polyimide layer. The first circuit is on a substrate. The capacitor includes a bottom plate over the substrate and a top plate over the bottom plate. The polyimide layer is at least partially over the top plate. A distance from a top surface of the top plate to a bottom surface of the polyimide layer is at least 30 % of a distance from a top surface of the bottom plate to a bottom surface of the top plate. A signal path, including the capacitor, is electrically coupled between the first circuit and a second circuit in the second IC die, which does not include a galvanic isolation capacitor in the signal path.

公开(公告)号：US11784212B2

公开(公告)日：2023-10-10

申请号：US17007726

申请日：2020-08-31

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield ,  Jeffrey Alan West ,  Byron Lovell Williams ,  Elizabeth Costner Stewart

IPC: H01L23/522 ,  H01L27/02 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L27/0292

Abstract: A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.

公开(公告)号：US20230047044A1

公开(公告)日：2023-02-16

申请号：US17403723

申请日：2021-08-16

Applicant: Texas Instruments Incorporated

Inventor： Elizabeth Stewart Costner ,  Jeffrey Alan West ,  Thomas Dyer Bonifield

IPC: H01L49/02 ,  H01G4/30 ,  H01L29/06

Abstract: A microelectronic device includes a semiconductor substrate and a high voltage isolation capacitor over the substrate. The capacitor includes a bottom capacitor plate over the substrate. Dielectric layers are formed above the bottom capacitor plate, including a top dielectric layer. A high dielectric layer on the top dielectric layer includes at least a first sublayer having a first dielectric constant that is higher than a dielectric constant of the top dielectric layer. A top capacitor plate is formed on the high dielectric layer over the bottom capacitor plate. An electric field abatement structure surrounds the top capacitor plate. The electric field abatement structure includes a shelf of the high dielectric layer extending outward from a lower corner of the bottom capacitor plate at least 14 microns, and an isolation break in the high dielectric layer past the shelf, in which the first sublayer is removed from the isolation break.

公开(公告)号：US11574995B2

公开(公告)日：2023-02-07

申请号：US17138059

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West

IPC: H01L49/02

Abstract: A method forms a first voltage node of a high voltage component of a microelectronic device. The method also forms a plurality of dielectric layers. The method also forms a second voltage node of the high voltage component of the microelectronic device in a fourth position such that the plurality of dielectric layers is between the first voltage node and the second voltage node. During the forming a second voltage node step, a portion of a third layer in the plurality of dielectric layers, in a region outwardly positioned relative to the second voltage node, is removed to expose the second layer, in the plurality of dielectric layers, in the region.

公开(公告)号：US20230005874A1

公开(公告)日：2023-01-05

申请号：US17364807

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Bo-Hsun Pan ,  Chien-Chang Li ,  Hung-Yu Chou ,  Shawn Martin O'Connor ,  Byron Lovell Williams ,  Jeffrey Alan West ,  Zi-Xian Zhan ,  Sheng-Wen Huang

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/495

Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions spaced from the die mount portion; a semiconductor die over the die mount portion having bond pads on an active surface facing away from the package substrate; non-gold bond wires forming electrical connections between at least one of the bond pads and one of the lead portions of the package substrate; a bond stitch on bump connection formed between one of the non-gold bond wires and a bond pad of the semiconductor die, comprising a stitch bond formed on a flex stud bump; and dielectric material covering a portion of the package substrate, the semiconductor die, the non-gold bond wires, the stitch bond and the flex stud bump, forming a packaged semiconductor device.

公开(公告)号：US20220231115A1

公开(公告)日：2022-07-21

申请号：US17152230

申请日：2021-01-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West ,  Byron Lovell Williams ,  Elizabeth Costner Stewart ,  Thomas Dyer Bonifeld

IPC: H01L49/02 ,  H01L23/552

Abstract: Described examples include a hybrid circuit having a component. The component has a first conductive element on a substrate having a configuration and having a first periphery and having an extension at the first periphery. The component also has a dielectric on the first conductive element. The component also has a second conductive element having the configuration on the dielectric that is proximate to and aligned with the first conductive element, and has a second periphery, the extension of the first conductive element extending past the second periphery.

公开(公告)号：US11227852B2

公开(公告)日：2022-01-18

申请号：US16854823

申请日：2020-04-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Honglin Guo ,  Jason Chien ,  Byron Lovell Williams ,  Jeffrey Alan West ,  Anderson Li ,  Arvin Nono Verdeflor

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L23/495 ,  H01L23/31 ,  H01L25/065

Abstract: An integrated circuit and methods for packaging the integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first integrated circuit die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first integrated circuit die and the palladium coated copper wires. The first integrated circuit die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.

公开(公告)号：US20200312794A1

公开(公告)日：2020-10-01

申请号：US16832356

申请日：2020-03-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West ,  Thomas Dyer Bonifield ,  Yoshihiro Takei ,  Mitsuhiro Sugimoto

IPC: H01L23/64 ,  H01L25/18

Abstract: A microelectronic device contains a high voltage component having an upper plate and a lower plate. The upper plate is isolated from the lower plate by a main dielectric between the upper plate and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the upper plate and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer of silicon nitride having a refractive index between 2.11 and 2.23. The lower-bandgap dielectric layer extends beyond the upper plate continuously around the upper plate. The lower-bandgap dielectric layer has an isolation break surrounding the upper plate at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the upper plate.