公开(公告)号：US09893008B2

公开(公告)日：2018-02-13

申请号：US15193355

申请日：2016-06-27

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield ,  Byron Williams ,  Shrinivasan Jaganathan ,  David Larkin ,  Dhaval Atul Saraiya

IPC: H05K1/09 ,  H01L23/522 ,  H05K1/03 ,  H05K1/16 ,  H01L23/62 ,  H05K1/02 ,  H05K3/46 ,  H05K3/00 ,  H05K1/11 ,  H01L23/498 ,  H01L23/528 ,  H01L23/532 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/5223 ,  H01L23/49811 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/538 ,  H01L23/62 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/14335 ,  H05K1/0256 ,  H05K1/0257 ,  H05K1/0262 ,  H05K1/0306 ,  H05K1/0346 ,  H05K1/09 ,  H05K1/112 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0088 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0175 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/0746 ,  H05K2201/09409 ,  H05K2201/0949 ,  H05K2201/09672 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

公开(公告)号：US09408302B2

公开(公告)日：2016-08-02

申请号：US14643230

申请日：2015-03-10

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield ,  Byron Williams ,  Shrinivasan Jaganathan ,  David Larkin ,  Dhaval Atul Saraiya

IPC: H05K1/09 ,  H05K1/03 ,  H05K1/16 ,  H01L23/62 ,  H05K1/02 ,  H05K3/46 ,  H05K3/00 ,  H05K1/11

CPC classification number: H01L23/5223 ,  H01L23/49811 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/538 ,  H01L23/62 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/14335 ,  H05K1/0256 ,  H05K1/0257 ,  H05K1/0262 ,  H05K1/0306 ,  H05K1/0346 ,  H05K1/09 ,  H05K1/112 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0088 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0175 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/0746 ,  H05K2201/09409 ,  H05K2201/0949 ,  H05K2201/09672 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

公开(公告)号：US20150187711A1

公开(公告)日：2015-07-02

申请号：US14576784

申请日：2014-12-19

Applicant: Texas Instruments Incorporated

Inventor： Licheng Marshal Han ,  Michael Andrew Serafin ,  Byron Williams ,  Sandra Rodriguez Varela ,  Salvatore Pavone

IPC: H01L23/00 ,  H01L23/50

CPC classification number: H01L23/562 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/56 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/78 ,  H01L21/784 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/5227 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/05 ,  H01L28/10 ,  H01L2224/02206 ,  H01L2224/02215 ,  H01L2224/05567 ,  H01L2224/94 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/35121 ,  H01L2224/03

Abstract: An integrated circuit and method with a delamination free opening formed through multiple levels of polymer dielectric. The opening has a vertical sidewall and no interface between adjacent levels of polymer dielectric is exposed on the vertical sidewall.

Abstract translation: 具有通过多层聚合物电介质形成的具有分层自由开口的集成电路和方法。 开口具有垂直侧壁，并且相邻层级的聚合物电介质之间没有界面暴露在垂直侧壁上。

公开(公告)号：US20240204040A1

公开(公告)日：2024-06-20

申请号：US18591587

申请日：2024-02-29

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey West ,  Mrinal Das ,  Byron Williams ,  Thomas Bonifield ,  Maxim Franke

IPC: H01G4/30 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L28/60 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49575 ,  H01L23/5223 ,  H01L23/5286 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2924/1426

Abstract: An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.

公开(公告)号：US11688760B2

公开(公告)日：2023-06-27

申请号：US17409080

申请日：2021-08-23

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey West ,  Mrinal Das ,  Byron Williams ,  Thomas Bonifield ,  Maxim Franke

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/52 ,  H01L23/495 ,  H01L23/31 ,  H01L49/02 ,  H01L23/00

CPC classification number: H01L28/60 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49513 ,  H01L23/49575 ,  H01L23/5223 ,  H01L23/5286 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2924/1426

Abstract: An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.

公开(公告)号：US20160133689A1

公开(公告)日：2016-05-12

申请号：US14931822

申请日：2015-11-03

Applicant: Texas Instruments Incorporated

Inventor： Honglin Guo ,  Tim A. Taylor ,  Jeff A. West ,  Ricky A. Jackson ,  Byron Williams

IPC: H01L49/02 ,  H01L23/29 ,  H01L21/02 ,  H01L23/31

CPC classification number: H01L21/02118 ,  H01G4/14 ,  H01G4/18 ,  H01G4/224 ,  H01G4/236 ,  H01G4/33 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/0228 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/564 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L28/40 ,  H01L51/00 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/04042 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/45099

Abstract: It has been discovered that poor TDDB reliability of microelectronic device capacitors with organic polymer material in the capacitor dielectric is due to water molecules infiltrating the organic polymer material when the microelectronic device is exposed to water vapor in the operating ambient. Water molecule infiltration from water vapor in the ambient is effectively reduced by a moisture barrier comprising a layer of aluminum oxide formed by an atomic layer deposition (ALD) process. A microelectronic device includes a capacitor with organic polymer material in the capacitor dielectric and a moisture barrier with a layer of aluminum oxide formed by an ALD process.

Abstract translation: 已经发现，在电容器电介质中的有机聚合物材料的微电子器件电容器的差的TDDB可靠性是由于当微电子器件在操作环境中暴露于水蒸汽时，水分子渗入有机聚合物材料。 通过包含由原子层沉积（ALD）工艺形成的氧化铝层的防潮屏障，水分子渗入环境中的水蒸气有效地减少。 微电子器件包括在电容器电介质中具有有机聚合物材料的电容器和具有由ALD工艺形成的氧化铝层的防潮层。

公开(公告)号：US20160133580A1

公开(公告)日：2016-05-12

申请号：US14854896

申请日：2015-09-15

Applicant: Texas Instruments Incorporated

Inventor： Thomas D. Bonifield ,  Jeffrey A. West ,  Byron Williams ,  Honglin Guo

IPC: H01L23/00 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L23/3171 ,  H01L23/585 ,  H01L23/62 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2924/00014 ,  H01L2924/3862 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

Abstract: A semiconductor die includes a plurality of layers, the plurality of layers having a top surface. A scribe seal is located in the plurality of layers and includes a first metal stack having a first metal layer located proximate the top surface. A trench is located in at least one layer of the plurality of layers. The trench extends from the top surface of the plurality of layers and is located a distance from the first metal stack. An electrical insulating layer is located on the top surface. The electrical insulating layer covers at least a portion of the top surface adjacent the first metal layer and extends a distance from the top surface of the first metal layer.

Abstract translation: 半导体管芯包括多个层，所述多个层具有顶表面。 划片密封件位于多个层中，并且包括具有位于顶表面附近的第一金属层的第一金属堆叠。 沟槽位于多层中的至少一层中。 沟槽从多个层的顶表面延伸并且距离第一金属叠层一定距离。 电绝缘层位于顶表面上。 电绝缘层覆盖与第一金属层相邻的顶表面的至少一部分，并从第一金属层的顶表面延伸一段距离。

公开(公告)号：US08890223B1

公开(公告)日：2014-11-18

申请号：US13960344

申请日：2013-08-06

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield ,  Byron Williams ,  Shrinivasan Jaganathan

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L29/00 ,  H01L49/02 ,  H01L27/02

CPC classification number: H01L28/60 ,  H01G4/10 ,  H01G4/14 ,  H01G4/206 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/06 ,  H01L27/0288 ,  H01L28/40 ,  H01L29/0642 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/0603 ,  H01L2224/48463 ,  H01L2924/13091 ,  H01L2924/00

Abstract: An integrated circuit includes isolation capacitors which include a silicon dioxide dielectric layer and a polymer dielectric layer over the layer of silicon dioxide. The silicon dioxide dielectric layer and the polymer dielectric layer extend across the integrated circuit. Top plates of the isolation capacitors have bond pads for wire bonds or bump bonds. Bottom plates of the isolation capacitors are connected to components of the integrated circuit. Other bond pads are connected to components in the integrated circuit through vias through the silicon dioxide dielectric layer and the polymer dielectric layer.

Abstract translation: 集成电路包括隔离电容器，其包括在二氧化硅层上的二氧化硅介电层和聚合物电介质层。 二氧化硅介电层和聚合物电介质层跨过集成电路延伸。 隔离电容器的顶板具有用于引线键合或凸起键的接合焊盘。 隔离电容器的底板连接到集成电路的组件。 其他接合焊盘通过通孔通过二氧化硅介电层和聚合物电介质层连接到集成电路中的组件。

公开(公告)号：US20230268377A1

公开(公告)日：2023-08-24

申请号：US18309999

申请日：2023-05-01

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey West ,  Mrinal Das ,  Byron Williams ,  Thomas Bonifield ,  Maxim Franke

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/495 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L28/60 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49575 ,  H01L23/5223 ,  H01L23/5286 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2924/1426

Abstract: An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.

公开(公告)号：US11961879B2

公开(公告)日：2024-04-16

申请号：US18309999

申请日：2023-05-01

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey West ,  Mrinal Das ,  Byron Williams ,  Thomas Bonifield ,  Maxim Franke

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/52 ,  H01L23/528 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49575 ,  H01L23/5223 ,  H01L23/5286 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2924/1426

Abstract: An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.