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公开(公告)号：US20210224065A1
公开(公告)日：2021-07-22
申请号：US17213509
申请日：2021-03-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
IPC: G06F9/30 , G06F9/38 , G06F11/10 , G06F9/32 , G06F12/0875 , G06F12/0897 , G06F11/00 , G06F9/345
Abstract: A steaming engine in a system receives a first set of stream parameters into a queue to define a first stream along with an indication of either a queue mode of operation or a speculative mode of operation for the first stream. Acquisition of the first stream then begins. At some point, a second set of stream parameters is received into the queue to define a second stream. When the queue mode of operation was specified for the first stream, the second set of parameters is queued and acquisition of the second stream is delayed until completion of acquisition of the first stream. When the speculative mode of operation was specified for the first stream, acquisition of the first stream is canceled upon receipt of the second set of stream parameters and acquisition of the second stream begins immediately.
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公开(公告)号：US20200319881A1
公开(公告)日：2020-10-08
申请号：US16852690
申请日：2020-04-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Timothy David Anderson , Duc Quang Bui , Mujibur Rahman , Joseph Raymond Michael Zbiciak , Eric Biscondi , Peter Dent , Jelena Milanovic , Ashish Shrivastava
Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.
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公开(公告)号：US10402199B2
公开(公告)日：2019-09-03
申请号：US14920298
申请日：2015-10-22
Applicant: Texas Instruments Incorporated
Abstract: One embodiment of this invention provides two conditional execution auxiliary instructions directed to disparate subsets of the plural functional units. Depending on the conditional execution desired, only one of the two conditional execution auxiliary instructions may be required for a particular execute packet. Another embodiment of this invention employs only one of two possible register files for the condition registers. In a VLIW processor it may be advantageous to split the functional units into separate sets with corresponding register files. This limits the number of functional units that may simultaneously access the register files. In the preferred embodiment of this invention the functional units are divided into a scalar set which access scalar registers and a vector set which access vector registers. The data registers storing the conditions for both scalar and vector instructions are in the scalar data register file.
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公开(公告)号：US20190187985A1
公开(公告)日：2019-06-20
申请号：US16282508
申请日：2019-02-22
Applicant: Texas Instruments Incorporated
IPC: G06F9/30 , G06F9/345 , G06F9/38 , G06F11/10 , G06F9/32 , G06F12/0875 , G06F12/0897 , G06F11/00
CPC classification number: G06F9/3016 , G06F9/30014 , G06F9/30036 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/3822 , G06F9/383 , G06F9/3867 , G06F11/00 , G06F11/10 , G06F11/1048 , G06F12/0875 , G06F12/0897 , G06F2212/452 , G06F2212/60
Abstract: Software instructions are executed on a processor within a computer system to configure a steaming engine to operate in either a linear mode or a transpose mode. A stream of addresses is generated using an address generator, in which the stream of addresses includes consecutive nested loop iterations for at least a first loop and a second loop. While in the linear mode, the first loop is treated as an inner loop. While in the transpose mode, the second loop is treated as the inner loop. A matrix can be fetched from memory in the linear mode to provide row-wise vectors. A matrix can be fetched from the memory in the transpose mode to provide column wise vectors. Local storage on the streaming engine is organized as sectors based on the number of rows in the matrix to allow overlapping transposition processing and to minimize memory accesses.
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公开(公告)号：US09965395B2
公开(公告)日：2018-05-08
申请号：US14874842
申请日：2015-10-05
Applicant: Texas Instruments Incorporated
Inventor： Raguram Damodaran , Joseph Raymond Michael Zbiciak , Naveen Bhoria
IPC: G06F12/00 , G06F12/0888 , G06F12/0897 , G06F12/12 , G06F12/0862
CPC classification number: G06F12/0888 , G06F12/0862 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F2212/1021 , G06F2212/6022 , G06F2212/70
Abstract: The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register.
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Patent Agency Ranking
56.发明申请公开(公告)号：US20150317259A1
公开(公告)日：2015-11-05
申请号：US14797859
申请日：2015-07-13
Applicant: Texas Instruments Incorporated
Inventor： Joseph Raymond Michael Zbiciak , Amitabh Menon
IPC: G06F12/14
CPC classification number: G06F12/1483 , G06F12/14 , G06F12/1425 , G06F12/1433 , G06F12/1441 , G06F12/1458 , G06F12/1491 , G06F13/366 , G06F21/78 , G06F21/79 , G06F2212/1052 , Y02D10/14
Abstract: A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the master, usually a CPU originating the request based on a Privilege Identifier that accompanies each memory access request. Deputy masters such as DMA controllers inherit the Privilege Identifier of the originating master. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the master originating the request.
Abstract translation: 一种管理来自多个请求者的存储器访问请求的存储器管理和保护系统。 基于主机的权限级别（通常是根据伴随每个存储器访问请求的权限标识符发起请求的CPU）允许或不允许内存访问。 诸如DMA控制器的副主人继承了始发主机的权限标识符。 扩展存储器控制器基于特权标识符选择适当的段寄存器集合，以确保请求被与发起请求的主机相关联的段寄存器进行比较和转换。
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公开(公告)号：US20250103510A1
公开(公告)日：2025-03-27
申请号：US18973226
申请日：2024-12-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Duc Quang Bui , Joseph Raymond Michael Zbiciak
IPC: G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/30 , G06F9/32 , G06F9/345 , G06F9/38 , G06F9/48 , G06F11/00 , G06F11/10 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F15/78 , G06F17/16 , H03H17/06
Abstract: In a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. The instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.
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公开(公告)号：US12105616B2
公开(公告)日：2024-10-01
申请号：US18354166
申请日：2023-07-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Joseph Raymond Michael Zbiciak , Jason Lynn Peck
CPC classification number: G06F11/3636 , G06F9/542
Abstract: Devices and methods are provided for identifying a debug event associated with a data element of a data stream, and performing debugging when a processor executes a software program in connection with the data stream. The debug event is tracked through a data pipeline to the processor. In an embodiment, the debug event is acted on only when the processor is ready to consume the data element associated with the debug event. In an embodiment, the debug event is determined by monitoring iteration counts of loop counters associated with an address generator and comparing the iteration counts to respective stored count values.
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公开(公告)号：US11900117B2
公开(公告)日：2024-02-13
申请号：US17213509
申请日：2021-03-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
IPC: G06F9/30 , G06F9/38 , G06F11/10 , G06F9/32 , G06F12/0875 , G06F12/0897 , G06F11/00 , G06F9/345
CPC classification number: G06F9/3016 , G06F9/3004 , G06F9/30014 , G06F9/30036 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/383 , G06F9/3842 , G06F9/3861 , G06F9/3867 , G06F9/3877 , G06F11/00 , G06F11/1048 , G06F12/0875 , G06F12/0897 , G06F9/3822 , G06F11/10 , G06F2212/452 , G06F2212/60
Abstract: A streaming engine in a system receives a first set of stream parameters into a queue to define a first stream along with an indication of either a queue mode of operation or a speculative mode of operation for the first stream. Acquisition of the first stream then begins. At some point, a second set of stream parameters is received into the queue to define a second stream. When the queue mode of operation was specified for the first stream, the second set of parameters is queued and acquisition of the second stream is delayed until completion of acquisition of the first stream. When the speculative mode of operation was specified for the first stream, acquisition of the first stream is canceled upon receipt of the second set of stream parameters and acquisition of the second stream begins immediately.
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公开(公告)号：US20230325189A1
公开(公告)日：2023-10-12
申请号：US18208444
申请日：2023-06-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
CPC classification number: G06F9/30167 , G06F9/3853 , G06F7/49994 , G06F9/3016 , G06F9/30181 , G06F9/3822
Abstract: In a very long instruction word (VLIW) central processing unit instructions are grouped into execute packets that execute in parallel. A constant may be specified or extended by bits in a constant extension instruction in the same execute packet. If an instruction includes an indication of constant extension, the decoder employs bits of a constant extension instruction to extend the constant of an immediate field. Two or more constant extension slots are permitted in each execute packet, each extending constants for a different predetermined subset of functional unit instructions. In an alternative embodiment, more than one functional unit may have constants extended from the same constant extension instruction employing the same extended bits. A long extended constant may be formed using the extension bits of two constant extension instructions.
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