公开(公告)号：US11500777B2

公开(公告)日：2022-11-15

申请号：US16775479

申请日：2020-01-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Ramakrishnan Venkatasubramanian

IPC: G06F12/0862 ,  G06F12/02 ,  G06F12/1027 ,  G06F12/0871 ,  G06F9/38

Abstract: Disclosed embodiments provide a technique in which a memory controller determines whether a fetch address is a miss in an L1 cache and, when a miss occurs, allocates a way of the L1 cache, determines whether the allocated way matches a scoreboard entry of pending service requests, and, when such a match is found, determine whether a request address of the matching scoreboard entry matches the fetch address. When the matching scoreboard entry also has a request address matching the fetch address, the scoreboard entry is modified to a demand request.

公开(公告)号：US11036648B2

公开(公告)日：2021-06-15

申请号：US16227238

申请日：2018-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Quang Bui ,  Abhijeet Chachad ,  Kai Chirca ,  Naveen Bhoria ,  Matthew D. Pierson ,  Daniel Wu ,  Ramakrishnan Venkatasubramanian

IPC: G06F9/34 ,  G06F11/00 ,  G06F12/0875 ,  G06F12/1045 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/1009

Abstract: Disclosed embodiments include a data processing apparatus having a processing core, a memory, and a streaming engine. The streaming engine is configured to receive a plurality of data elements stored in the memory and to provide the plurality of data elements as a data stream to the processing core, and includes an address generator to generate addresses corresponding to locations in the memory, a buffer to store the data elements received from the locations in the memory corresponding to the generated addresses, and an output to supply the data elements received from the memory to the processing core as the data stream.

公开(公告)号：US20190179759A1

公开(公告)日：2019-06-13

申请号：US16279721

申请日：2019-02-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Ramakrishnan Venkatasubramanian

IPC: G06F12/0862 ,  G06F12/1027 ,  G06F12/02 ,  G06F9/38

Abstract: Disclosed embodiments provide a technique in which a memory controller determines whether a fetch address is a miss in an L1 cache and, when a miss occurs, allocates a way of the L1 cache, determines whether the allocated way matches a scoreboard entry of pending service requests, and, when such a match is found, determine whether a request address of the matching scoreboard entry matches the fetch address. When the matching scoreboard entry also has a request address matching the fetch address, the scoreboard entry is modified to a demand request.

公开(公告)号：US09798344B2

公开(公告)日：2017-10-24

申请号：US15236743

申请日：2016-08-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ramakrishnan Venkatasubramanian ,  Shane Stelmach ,  Soman Purushotaman ,  Michael Gill ,  Jose Luis Flores

IPC: G05F1/10 ,  G05F3/02 ,  H03K17/687

CPC classification number: G05F3/02 ,  H03K17/6871 ,  H03K17/6872

Abstract: This invention is an electronic circuit with a low power retention mode. A single integrated circuit includes a circuit module and a droop switch circuit supplied by a voltage regulator. In a normal mode a PMOS source-drain channel connects the voltage regulator power to the circuit module power input or isolates them dependent upon a power switch input. In a low power mode a second PMOS connected between the first PMOS gate and output diode connects the first PMOS. This supplied the circuit module from the voltage regulator power as reduced in voltage by a diode forward bias drop. This lower voltage should be sufficient for flip-flops in the circuit module to retain their state while not guaranteeing logic operation. There may be a plurality of chain connected droop switch each powering a corresponding circuit module.

公开(公告)号：US20170153890A1

公开(公告)日：2017-06-01

申请号：US15429205

申请日：2017-02-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Quang Bui ,  Abhijeet A. Chachad ,  Kai Chirca ,  Naveen Bhoria ,  Matthew D. Pierson ,  Daniel Wu ,  Ramakrishnan Venkatasubramanian

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897

CPC classification number: G06F9/3016 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3822 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/10 ,  G06F11/1048 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/452 ,  G06F2212/60

Abstract: This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.

公开(公告)号：US09652392B2

公开(公告)日：2017-05-16

申请号：US15270018

申请日：2016-09-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ramakrishnan Venkatasubramanian ,  Oluleye Olorode ,  Hung Ong

IPC: G06F12/08 ,  G06F9/38 ,  G06F12/0817 ,  G06F12/0811 ,  G06F12/0804 ,  G06F12/0875 ,  G06F12/0897

CPC classification number: G06F12/0828 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/38 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3873 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/621

Abstract: A method is shown that eliminates the need for a dedicated reorder buffer register bank or memory space in a multi level cache system. As data requests from the L2 cache may be returned out of order, the L1 cache uses it's cache memory to buffer the out of order data and provides the data to the requesting processor in the correct order from the buffer.

公开(公告)号：US09417648B1

公开(公告)日：2016-08-16

申请号：US14733286

申请日：2015-06-08

Applicant: Texas Instruments Incorporated

Inventor： Ramakrishnan Venkatasubramanian ,  Shane Stelmach ,  Soman Purushotaman ,  Michael Gill ,  Jose Luis Flores

IPC: G05F1/10 ,  G05F3/02 ,  H03K17/687

CPC classification number: G05F3/02 ,  H03K17/6871 ,  H03K17/6872

Abstract: This invention is an electronic circuit with a low power retention mode. A single integrated circuit includes a circuit module and a droop switch circuit supplied by a voltage regulator. In a normal mode a PMOS source-drain channel connects the voltage regulator power to the circuit module power input or isolates them dependent upon a power switch input. In a low power mode a second PMOS connected between the first PMOS gate and output diode connects the first PMOS. This supplied the circuit module from the voltage regulator power as reduced in voltage by a diode forward bias drop. This lower voltage should be sufficient for flip-flops in the circuit module to retain their state while not guaranteeing logic operation. There may be a plurality of chain connected droop switch each powering a corresponding circuit module.

Abstract translation: 本发明是具有低功率保持模式的电子电路。 单个集成电路包括由电压调节器提供的电路模块和下垂开关电路。 在正常模式下，PMOS源极 - 漏极通道将电压调节器功率连接到电路模块电源输入，或者根据电源开关输入将其隔离。 在低功率模式中，连接在第一PMOS栅极和输出二极管之间的第二PMOS连接第一PMOS。 这通过二极管正向偏压下降，从电压调节器电源提供电压降低的电压。 这个较低的电压应该足以使电路模块中的触发器保持其状态而不保证逻辑运行。 可以有多个链式连接的下垂开关，各自为对应的电路模块供电。