公开(公告)号：US07521324B2

公开(公告)日：2009-04-21

申请号：US10551843

申请日：2004-03-31

申请人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Hidetoshi Wakamatsu ,  Yasuo Kobayashi

发明人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Hidetoshi Wakamatsu ,  Yasuo Kobayashi

IPC分类号： H01L21/336

CPC分类号： H01L21/318 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518

摘要： In order to provide a semiconductor device having good quality by keeping the relative permittivity of a High-K insulation film in a high state, or to provide a method for manufacturing a semiconductor device in which the relative permittivity of the High-K insulation film can be kept in a high state, a semiconductor device is disclosed that includes a silicon substrate, a gate electrode layer, and a gate insulation film between the silicon substrate and the gate electrode layer. The gate insulation film is a high relative permittivity (high-k) film being formed by performing a nitriding treatment on a mixture of a metal and silicon. The High-K film itself becomes a nitride so as to prevent SiO2 from being formed.

摘要翻译： 为了通过将高K绝缘膜的相对介电常数保持在高状态来提供具有良好质量的半导体器件，或者提供一种半导体器件的制造方法，其中高K绝缘膜的相对介电常数可以 保持在高状态，公开了在硅衬底和栅极电极层之间包括硅衬底，栅极电极层和栅极绝缘膜的半导体器件。 栅极绝缘膜是通过对金属和硅的混合物进行氮化处理而形成的高相对介电常数（高k）膜。 高K膜本身成为氮化物，以防止形成SiO 2。

公开(公告)号：US20080054795A1

公开(公告)日：2008-03-06

申请号：US11663560

申请日：2004-09-24

申请人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Akihiro Morimoto

发明人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Akihiro Morimoto

IPC分类号： H01L51/54 ,  H01J63/04 ,  H05H1/24 ,  H05H1/46

CPC分类号： H05B33/28 ,  H01L51/5206 ,  H01L51/5253 ,  H01L51/529 ,  H01L2251/5361 ,  H05B33/04

摘要： An organic EL light emitting element is provided with a conductive transparent electrode 3, a counter electrode 8 opposing the conductive transparent electrode 3, an organic EL light emitting layer 6 provided between the conductive transparent electrode 3 and the counter electrode 8, an insulating protection layer 9 provided to cover at least the organic EL light emitting layer 6, and a heat dissipating layer 11 which is brought into contact with the insulating protection layer 9. The conductive transparent electrode has an ITO film including at least one of Hf, V and Zr at least on the surface part on the side of the organic EL light emitting layer 6, and the insulating protection layer 9 includes a nitride film having a thickness of 100 nm or less.

摘要翻译： 有机EL发光元件设置有导电透明电极3，与导电透明电极3相对的对置电极8，设置在导电性透明电极3和对置电极8之间的有机EL发光层6，绝缘保护层 设置为至少覆盖有机EL发光层6，以及与绝缘保护层9接触的散热层11。 导电性透明电极至少在有机EL发光层6侧的表面部分具有包括Hf，V和Zr中的至少一种的ITO膜，绝缘保护层9包括厚度为 100nm以下。

公开(公告)号：US20070145535A1

公开(公告)日：2007-06-28

申请号：US11651034

申请日：2007-01-09

申请人： Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Akinobu Teramoto ,  Hiroshi Akahori ,  Keiichi Nii

发明人： Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Akinobu Teramoto ,  Hiroshi Akahori ,  Keiichi Nii

IPC分类号： H01L29/06

CPC分类号： H01L21/3185 ,  H01L21/30604 ,  H01L21/31654 ,  H01L21/318 ,  H01L29/6659

摘要： In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.

摘要翻译： 在形成在具有大致（110）晶面取向的硅表面上的半导体器件中，硅表面变平，使得表面Ra的算术平均偏差不大于0.15nm，优选为0.09nm，这使得能够制造 高迁移率的n-MOS晶体管。 通过在脱氧H 2中清洗硅表面，通过在氧自由基气氛中重复自牺牲氧化物膜的沉积工艺和自牺牲氧化物膜的去除工艺来获得这种扁平化的硅表面， 或低OH密度气氛，或通过氢或重氢强烈地终止硅表面。 自牺牲氧化膜的沉积工艺可以通过各向同性氧化进行。

公开(公告)号：US20070142017A1

公开(公告)日：2007-06-21

申请号：US10560398

申请日：2004-06-11

申请人： Takefumi Nishimuta ,  Hiroshi Miyagi ,  Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Akinobu Teramoto

发明人： Takefumi Nishimuta ,  Hiroshi Miyagi ,  Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Akinobu Teramoto

IPC分类号： H04B1/26 ,  H04B1/28

CPC分类号： H01L29/1033 ,  H01L21/823807 ,  H01L21/82385 ,  H01L29/045 ,  H03D7/1441 ,  H03D7/1458 ,  H03D2200/0033 ,  H03D2200/0047

摘要： A mixer circuit is configured using a CMOS transistor (800), comprising a p-channel transistor (840A) and an n-channel transistor (840B) in which semiconductor substrates (810A, 810) with at least two crystal planes and a gate insulator (820A) formed on at least two of the crystal planes on the semiconductor substrate are comprised and the channel width of a channel formed in the semiconductor substrate along with the gate insulator is represented by summation of each of the channel widths of channels individually formed on said at least two crystal planes. Such a configuration allows reduction of 1/f noise, DC offset generated in output signals due to variation in electrical characteristics of a transistor element, and signal distortion based on the channel length modulation effect.

摘要翻译： 使用CMOS晶体管（800）构成混频器电路，其包括p沟道晶体管（840A）和n沟道晶体管（840B），其中具有至少两个晶体面的半导体衬底（810A，810）和 包括形成在半导体衬底上的至少两个晶面上的栅极绝缘体（820A），并且与栅极绝缘体一起形成在半导体衬底中的沟道的沟道宽度由每个沟道宽度的和 在所述至少两个晶面上分别形成的通道。 这样的配置允许减少由于晶体管元件的电特性的变化而在输出信号中产生的1 / f噪声，DC偏移以及基于沟道长度调制效应的信号失真。

公开(公告)号：US20070023780A1

公开(公告)日：2007-02-01

申请号：US10558760

申请日：2004-05-31

申请人： Tadahiro Ohmi ,  Akinobu Teramoto

发明人： Tadahiro Ohmi ,  Akinobu Teramoto

IPC分类号： H01L31/00

CPC分类号： H01L21/82385 ,  H01L21/28167 ,  H01L21/823857 ,  H01L29/66787 ,  H01L29/785

摘要： A gate insulating film is formed using a plasma on a three-dimensional silicon substrate surface having a plurality of crystal orientations. The plasma gate insulating film experiences no increase in interface state in any crystal orientations as compared with tat in Si (100) crystal orientation and has a uniform thickness even at corner portions of the three-dimensional structure. By forming a high-quality gate insulating film using a plasma, there can be obtained a semiconductor device having good characteristics.

摘要翻译： 在具有多个晶体取向的三维硅衬底表面上使用等离子体形成栅极绝缘膜。 与Si（100）晶体取向相比，等离子体栅极绝缘膜在任何晶体取向上的界面态没有增加，即使在三维结构的角部也具有均匀的厚度。 通过使用等离子体形成高品质的栅极绝缘膜，可以获得具有良好特性的半导体器件。

公开(公告)号：US20060264059A1

公开(公告)日：2006-11-23

申请号：US10568461

申请日：2004-08-12

申请人： Yasuo Kobayashi ,  Kohei Kawamura ,  Tadahiro Ohmi ,  Akinobu Teramoto ,  Tatsuya Sugimoto ,  Toshiro Yamada ,  Kimiaki Tanaka

发明人： Yasuo Kobayashi ,  Kohei Kawamura ,  Tadahiro Ohmi ,  Akinobu Teramoto ,  Tatsuya Sugimoto ,  Toshiro Yamada ,  Kimiaki Tanaka

IPC分类号： H01L23/58 ,  H01L21/31

CPC分类号： H01L21/3127 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/3146

摘要： The present invention relates to a semiconductor device comprising an insulation film consisting of a fluoridation carbon film that has been subjected to thermal history of 420° C. or lower. The feature of the present invention is that an amount of hydrogen atoms included in the fluoridation carbon film is 3 atomic % or less before the fluoridation carbon film is subjected to the thermal history.

摘要翻译： 本发明涉及一种半导体器件，其包括由经历420℃或更低的热历史的氟化碳膜构成的绝缘膜。 本发明的特征在于，在氟化碳膜经受热历史之前，包含在氟化碳膜中的氢原子数量为3原子％以下。

公开(公告)号：US20060051934A1

公开(公告)日：2006-03-09

申请号：US10544491

申请日：2004-02-02

申请人： Tadahiro Ohmi ,  Akinobu Teramoto

发明人： Tadahiro Ohmi ,  Akinobu Teramoto

IPC分类号： H01L21/30

CPC分类号： H01L21/76256

摘要： An insulating film is formed as a pore-wall protective film (103) on pore walls in a porous layer (102) by the use of a mixed gas plasma of a noble gas and an insulating film forming gas generated by microwave excitation. As a result, the pore-wall protective film can have film properties as a protective film.

摘要翻译： 通过使用惰性气体的混合气体等离子体和通过微波激发产生的形成绝缘膜的气体，在多孔层（102）的孔壁上形成绝缘膜作为孔壁保护膜（103）。 结果，孔壁保护膜可以具有作为保护膜的膜性质。

公开(公告)号：US09157681B2

公开(公告)日：2015-10-13

申请号：US13565868

申请日：2012-08-03

申请人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Tomoyuki Suwa

发明人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Tomoyuki Suwa

IPC分类号： H01L29/06 ,  F27B17/00 ,  H01L21/02 ,  H01L21/302 ,  H01L21/67 ,  H01L21/677 ,  H01L21/324

CPC分类号： H01L21/3247 ,  F27B17/0025 ,  H01L21/02052 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/302 ,  H01L21/67017 ,  H01L21/67109 ,  H01L21/67126 ,  H01L21/67757

摘要： In a silicon wafer which has a surface with a plurality of terraces formed stepwise by single-atomic-layer steps, respectively, no slip line is formed.

摘要翻译： 在具有分别通过单原子层阶梯逐步形成的多个台阶的表面的硅晶片中，不形成滑移线。

公开(公告)号：US08399862B2

公开(公告)日：2013-03-19

申请号：US12521019

申请日：2007-12-20

申请人： Tadahiro Ohmi ,  Tetsuya Goto ,  Akinobu Teramoto ,  Takaaki Matsuoka

发明人： Tadahiro Ohmi ,  Tetsuya Goto ,  Akinobu Teramoto ,  Takaaki Matsuoka

IPC分类号： G21K5/10 ,  H01S3/00 ,  H05H3/02 ,  A61N5/00 ,  G21G5/00 ,  G21G4/00

CPC分类号： H01L21/265 ,  H01J37/3222 ,  H01J37/32412 ,  H01J37/32706 ,  H01J2237/20 ,  H01J2237/26 ,  H01L21/26513 ,  H01L21/2658 ,  H01L29/30 ,  H01L29/7833

摘要： When positively charged ions are implanted into a target substrate, charge-up damage may occur on the target substrate. In order to suppress charge-up caused by secondary electrons emitted from the target substrate when positively charged ions are implanted, a conductive member is installed at a position facing the target substrate and electrically grounded with respect to a high frequency. Further, a field intensity generated in the target substrate may be reduced by controlling an RF power applied to the target substrate in pulse mode.

摘要翻译： 当将带正电荷的离子注入目标衬底时，目标衬底上可能会发生充电损伤。 为了抑制当注入正电荷的离子时从目标衬底发射的二次电子引起的充电，导电构件安装在面向目标衬底并相对于高频电接地的位置。 此外，可以通过以脉冲模式控制施加到目标衬底的RF功率来减小在目标衬底中产生的场强。

公开(公告)号：US08217270B2

公开(公告)日：2012-07-10

申请号：US11990860

申请日：2006-08-18

申请人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Akihiro Morimoto

发明人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Akihiro Morimoto

IPC分类号： H05K1/03

CPC分类号： H05K1/024 ,  H05K3/4602 ,  H05K3/4626 ,  H05K3/4673 ,  H05K2201/0116 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0254

摘要： A multilayered circuit board which is provided with a low-permittivity interlayer insulating film, and which can significantly improve the performance such as signal transmission characteristics of the multilayered circuit board such as a package and a printed board, because the surface in contact with the interlayer insulating film of the circuit board has no unevenness to eliminate the lowering of production yield and the deterioration of high-frequency signal transmission characteristics; and electronic equipment using the circuit board. The multilayered circuit board comprises, mounted on a substrate, plural wiring layers and plural insulating layers positioned between the plural wiring layers, wherein at least part of the plural insulating layers are composed of a porous insulating layer containing at least any of materials selected from a porous material group consisting of porous material, aerogel, porous silica, porous polymer, hollow silica and hollow polymer, and a non-porous insulating layer formed on at least one surface of the porous insulating layer and not containing the porous material group.

摘要翻译： 具有低介电常数层间绝缘膜的多层电路板，能够显着地提高诸如封装和印刷电路板的多层电路板的信号传输特性等性能，因为与中间层 电路板的绝缘膜没有不均匀性，消除了生产成本的降低和高频信号传输特性的恶化; 和使用电路板的电子设备。 多层电路板包括安装在基板上的多个布线层和位于多个布线层之间的多个绝缘层，其中多个绝缘层的至少一部分由多孔绝缘层组成，多孔绝缘层至少含有选自 由多孔材料，气凝胶，多孔二氧化硅，多孔聚合物，中空二氧化硅和中空聚合物组成的多孔材料组和形成在多孔绝缘层的至少一个表面上并且不包含多孔材料组的无孔绝缘层。