公开(公告)号：US20230395588A1

公开(公告)日：2023-12-07

申请号：US18447655

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Ying-Ju Chen ,  Hsien-Wei Chen

IPC: H01L25/00 ,  H01L21/78 ,  H01L21/683 ,  H01L23/31 ,  H01L23/58 ,  H01L23/498 ,  H01L23/538 ,  H01L23/544 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/12

CPC classification number: H01L25/50 ,  H01L21/78 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/585 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L21/56 ,  H01L21/76838 ,  H01L23/12 ,  H01L23/562 ,  H01L24/06 ,  H01L21/565 ,  H01L21/561 ,  H01L21/568 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2221/68372 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2225/06568 ,  H01L24/32 ,  H01L24/48 ,  H01L25/105

Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.

公开(公告)号：US11817445B2

公开(公告)日：2023-11-14

申请号：US17687911

申请日：2022-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Ying-Ju Chen ,  Hsien-Wei Chen

IPC: H01L21/44 ,  H01L25/00 ,  H01L21/78 ,  H01L21/683 ,  H01L23/31 ,  H01L23/58 ,  H01L23/498 ,  H01L23/538 ,  H01L23/544 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/12 ,  H01L25/10

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/12 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L23/562 ,  H01L23/585 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L24/32 ,  H01L24/48 ,  H01L25/105 ,  H01L2221/68372 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/97 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2224/85399

Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.

公开(公告)号：US20220302069A1

公开(公告)日：2022-09-22

申请号：US17833034

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Ju Chen ,  An-Jhih Su ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L25/10

Abstract: A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.

公开(公告)号：US20220301890A1

公开(公告)日：2022-09-22

申请号：US17328001

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Ying-Ju Chen

IPC: H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538

Abstract: A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.

公开(公告)号：US20210151389A1

公开(公告)日：2021-05-20

申请号：US17140734

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Ying-Ju Chen ,  Hsien-Wei Chen

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die.

公开(公告)号：US20210098423A1

公开(公告)日：2021-04-01

申请号：US16737856

申请日：2020-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ching-Jung Yang ,  Ming-Fa Chen ,  Sung-Feng Yeh ,  Ying-Ju Chen

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/768

Abstract: A package structure includes a first die, a second die, an insulation structure, a through via, a dielectric layer and a redistribution layer. The second die is electrically bonded to the first die. The insulation structure is disposed on the first die and laterally surrounds the second die. The through via penetrates through the insulation structure to electrically connect to the first die. The through via includes a first barrier layer and a conductive post on the first barrier layer. The dielectric layer is on the second die and the insulation structure. The redistribution layer is embedded in the dielectric layer and electrically connected to the through via. The redistribution layer includes a second barrier layer and a conductive layer on the second barrier layer. The conductive layer of the redistribution layer is in contact with the conductive post of the through via.

公开(公告)号：US10923421B2

公开(公告)日：2021-02-16

申请号：US16391309

申请日：2019-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Ju Chen ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L21/56 ,  H01L21/768 ,  H01L25/065

Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and a connection pad. The redistribution circuit structure is located on and electrically connected to the semiconductor die. The connection pad is embedded in and electrically connected to the redistribution circuit structure, and the connection pad includes a barrier film and a conductive pattern underlying thereto, where a surface of the barrier film is substantially leveled with an outer surface of the redistribution circuit structure.

公开(公告)号：US20200343183A1

公开(公告)日：2020-10-29

申请号：US16391309

申请日：2019-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Ju Chen ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L21/56 ,  H01L21/768 ,  H01L25/065

Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and a connection pad. The redistribution circuit structure is located on and electrically connected to the semiconductor die. The connection pad is embedded in and electrically connected to the redistribution circuit structure, and the connection pad includes a barrier film and a conductive pattern underlying thereto, where a surface of the barrier film is substantially levelled with an outer surface of the redistribution circuit structure.

公开(公告)号：US10504852B1

公开(公告)日：2019-12-10

申请号：US16016658

申请日：2018-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ying-Ju Chen

IPC: H01L23/544 ,  H01L23/522 ,  H01L25/065 ,  H01L23/528

Abstract: Three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure includes a first die and a second die bonded to the first die. The first die includes a first integrated circuit region and a first seal ring region around the first integrated circuit region, and has a first alignment mark within the first integrated circuit region. The second die includes a second integrated circuit region and a second seal ring region around the second integrated circuit region, and has a second alignment mark within the second seal ring region and corresponding to the first alignment mark.

公开(公告)号：US20190067001A1

公开(公告)日：2019-02-28

申请号：US15884328

申请日：2018-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Tzuan-Horng Liu ,  Ying-Ju Chen

IPC: H01L21/027 ,  H01L23/498 ,  H01L23/544 ,  H01L23/00

Abstract: A first mask and a second mask are sequentially provided to perform a multi-step exposure and development processes. Through proper overlay design of the first mask and the second mask, conductive wirings having acceptable overlay offset are formed.