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    Manufacturing system for microstructure
    53.
    发明申请
    Manufacturing system for microstructure 审中-公开
    微结构制造系统

    公开(公告)号：US20050229737A1

    公开(公告)日：2005-10-20

    申请号：US11060767

    申请日：2005-02-18

    申请人： Takeshi Tsuno ,  Takayuki Goto ,  Satoshi Tawara ,  Masato Kinouchi ,  Shin Asano ,  Osamu Hasegawa ,  Takayuki Yamada ,  Mutsuya Takahashi

    发明人： Takeshi Tsuno ,  Takayuki Goto ,  Satoshi Tawara ,  Masato Kinouchi ,  Shin Asano ,  Osamu Hasegawa ,  Takayuki Yamada ,  Mutsuya Takahashi

    IPC分类号： B81C3/00 ,  B29C65/00 ,  B81C99/00 ,  G05G11/00

    CPC分类号： B29C65/002 ,  B29C64/35 ,  B29C65/006 ,  B29C65/7817 ,  B29C66/0222 ,  B29C66/028 ,  B29C66/73161 ,  B29C66/7352 ,  B29C66/9672 ,  B29K2995/0072 ,  Y10T74/20354

    摘要： A manufacturing system for a microstructure includes a rough motion stage having predetermined positioning accuracy and a large stroke length, a fine motion stage disposed on the rough motion stage and having higher positioning accuracy than the rough motion stage and a small stroke length, and the like collectively as a stage device disposed in a vacuum container, laser length measuring machines for measuring a distance to a mirror disposed on the fine motion stage, a stage control device for driving the fine motion stage by a result of measurement by the laser length measuring machines, and the like collectively as a stage control unit, and a pressing rod 44 for holding a pressure-contacting target member disposed opposite to a pressure-contacted member held by the stage device and pressure-contacting and separating the members, a pressure-contacting drive mechanism for applying a pressure-contacting force to the pressing rod 44, and the like collectively as a pressure-contacting mechanism unit.

    摘要翻译： 用于微结构的制造系统包括具有预定定位精度和大行程长度的粗动作台，设置在粗动台上的精细动作台，具有比粗动作台高的定位精度和较小的行程长度等 统称为设置在真空容器中的舞台装置，用于测量与配置在微动平台上的镜子的距离的激光长度测量机，用于通过激光长度测量机测量结果驱动微动台的舞台控制装置 等等作为台架控制单元，以及按压杆44，用于保持与由台架装置保持的压接构件相对设置的受压接触目标构件，并且对构件进行压力接触和分离，压力接触 驱动机构，用于将压力接触力一体地作为压力接触mec施加到按压杆44等 汉族单位。

    Socket for electrical parts having separable plunger
    54.
    发明授权
    Socket for electrical parts having separable plunger 失效
    具有可分离柱塞的电气部件插座

    公开(公告)号：US06743043B2

    公开(公告)日：2004-06-01

    申请号：US10075764

    申请日：2002-02-15

    申请人： Takayuki Yamada

    发明人： Takayuki Yamada

    IPC分类号： H01R1118

    CPC分类号： H01R13/2421 ,  G01R1/0483 ,  G01R1/06722 ,  H01R2201/20

    摘要： A socket for an electrical part comprises a socket body and a contact pin through which an electrical part having a terminal and a printed circuit board are electrically connected. The socket body is provided with a lower plate to be mounted to the printed circuit board and an upper plate which is disposed above the lower plate and on which the electrical part is mounted. The upper plate is exchanged with one having a seating portion of different height. A contact portion of the contact pin is also exchangeable with one having different shape or type.

    摘要翻译： 用于电气部件的插座包括插座主体和接触销，电连接端子和印刷电路板的电气部件通过该插座主体和接触销。 插座主体设置有要安装到印刷电路板的下板和设置在下板上方并且电气部件安装在其上的上板。 上板更换为具有不同高度的座位部分。 接触销的接触部分也可以与具有不同形状或类型的接触部分交换。

    APPARATUS AND METHOD FOR OPTICAL EVALUATION, APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF CONTROLLING APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
    55.
    发明授权
    APPARATUS AND METHOD FOR OPTICAL EVALUATION, APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF CONTROLLING APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE 失效
    用于光学评估的装置和方法，制造半导体器件的装置和方法，用于制造半导体器件的控制装置的方法和半导体器件

    公开(公告)号：US06580091B1

    公开(公告)日：2003-06-17

    申请号：US09610432

    申请日：2000-07-05

    申请人： Koji Eriguchi ,  Takayuki Yamada ,  Masanori Okuyama

    发明人： Koji Eriguchi ,  Takayuki Yamada ,  Masanori Okuyama

    IPC分类号： H01L2358

    CPC分类号： H01L21/3065

    摘要： A top surface of a wafer is provided with an n-type source region, an n-type drain region, and an n-type semiconductor region. Dry etching using a plasma is performed with respect to an interlayer insulating film deposited on the wafer to form openings reaching the respective regions, followed by light etching for removing a damaged layer. In this case, exciting light is supplied intermittently to the n-type semiconductor region. The progression of the removal of the damaged layer and the stage of development of a newly damaged layer are sensed by monitoring the change rate of the intensity of reflected probe light in the presence and absence of the exciting light, resulting in the formation of a semiconductor device having low and equal contact resistance. In-line control using optical evaluation enables the implementation of semiconductor devices with excellent and consistent properties.

    摘要翻译： 晶片的顶表面设置有n型源极区，n型漏极区和n型半导体区。 对沉积在晶片上的层间绝缘膜进行使用等离子体的干蚀刻，以形成到达各个区域的开口，然后进行光蚀刻以去除损伤层。 在这种情况下，向n型半导体区域间歇地供给激发光。 通过在存在和不存在激发光的情况下监测反射的探测光的强度的变化率来检测损坏层的去除进展和新损坏层的显影阶段，导致形成半导体 器件具有低和相等的接触电阻。 使用光学评估的在线控制使得能够实现具有优异和一致特性的半导体器件。

    Socket for electrical parts
    56.
    发明授权
    Socket for electrical parts 失效
    电气部件插座

    公开(公告)号：US06533595B2

    公开(公告)日：2003-03-18

    申请号：US09258035

    申请日：1999-02-25

    申请人： Takayuki Yamada

    发明人： Takayuki Yamada

    IPC分类号： H01R1122

    CPC分类号： H05K7/1023

    摘要： A socket, such as IC socket, for an electrical part such as IC package comprises a socket body having a mount portion on which an electrical part having terminals is mounted, a plurality of contact pins arranged to the socket body and having an elastic property adapted to contact and separate from the terminals of the electrical part, and an upper operation member arranged for the socket body to be vertically movable in a mounted state and having substantially a rectangular frame shape. Each of the contact pins is formed with a movable contact piece contacting the terminal of the electrical part, and the movable contact pin is deformed by the vertical movement of the operation member so as to contact and separate from the terminal. At least one of the operation member and the socket body is provided with a deformation restriction means, and the deformation restriction means is adapted to abut against at least another one of the operation member and the socket body at a time when the operation member takes most lowered position and restrict inward or outward deformation of the operation member due to a replusive force of the contact pin.

    摘要翻译： 诸如IC封装的电气部件的诸如IC插座的插座包括具有安装部分的插座主体，其上安装有端子的电气部件，多个接触销布置到插座主体并具有适应性的弹性 与电气部件的端子接触和分离，以及布置成用于插座主体的上部操作构件，其可以在安装状态下垂直移动并且具有基本上矩形的框架形状。 每个接触针形成有与电气部件的端子接触的可动接触片，并且可动接触销通过操作构件的垂直移动而变形，以便与端子接触和分离。 操作构件和插座主体中的至少一个设置有变形限制装置，并且变形限制装置适于在操作构件最多占用时抵靠操作构件和插座主体中的至少另一个 降低位置并且由于接触销的重复力而限制操作构件的向内或向外变形。

    Semiconductor device and method of manufacturing the same
    58.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06333223B1

    公开(公告)日：2001-12-25

    申请号：US09433221

    申请日：1999-11-04

    申请人： Masaru Moriwaki ,  Takayuki Yamada

    发明人： Masaru Moriwaki ,  Takayuki Yamada

    IPC分类号： H01L218242

    CPC分类号： H01L27/11526 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11539 ,  H01L29/66545

    摘要： A semiconductor device comprises a first MOSFET and a second MOSFET. The first MOSFET includes a first gate insulating film formed on a semiconductor substrate and having a relatively large thickness and a first gate electrode composed of a polysilicon film formed on the first gate insulating film. The second MOSFET includes a second gate insulating film formed on the semiconductor substrate and having a relatively small thickness and a second gate electrode composed of a metal film made of a refractory metal or a compound of a refractory metal and formed on the second gate insulating film.

    摘要翻译： 半导体器件包括第一MOSFET和第二MOSFET。 第一MOSFET包括形成在半导体衬底上并且具有相对较大厚度的第一栅极绝缘膜和由形成在第一栅极绝缘膜上的多晶硅膜构成的第一栅电极。 第二MOSFET包括形成在半导体衬底上并且具有相对较小厚度的第二栅极绝缘膜和由难熔金属或难熔金属化合物制成的金属膜构成的第二栅极，并形成在第二栅极绝缘膜上 。

    MIS device, method of manufacturing the same, and method of diagnosing the same
    59.
    发明授权
    MIS device, method of manufacturing the same, and method of diagnosing the same 失效
    MIS装置及其制造方法及其诊断方法

    公开(公告)号：US5903031A

    公开(公告)日：1999-05-11

    申请号：US675659

    申请日：1996-07-03

    申请人： Takayuki Yamada ,  Takashi Nakabayashi ,  Masatoshi Arai ,  Toshiki Yabu ,  Koji Eriguchi

    发明人： Takayuki Yamada ,  Takashi Nakabayashi ,  Masatoshi Arai ,  Toshiki Yabu ,  Koji Eriguchi

    IPC分类号： H01L21/3213 ,  H01L21/768 ,  H01L29/78

    CPC分类号： H01L21/76838 ,  H01L21/32136

    摘要： In a first region of a semiconductor substrate, there are formed MIS transistors each composed of a gate insulating film, a gate electrode, and source/drain regions. In a second region of the semiconductor substrate, there is formed an impurity diffusion layer serving as a conductive layer. On an interlayer insulating film, there are formed an antenna interconnection connected to the gate electrodes and an interconnection for charge dissipation connected to the conductive layer. During the process of dry etching for forming the interconnections, charges move into the semiconductor substrate via the interconnection for charge dissipation. The deterioration of the gate insulating film caused by the injection of charges into the gate electrode is suppressed and the degradation of characteristics of the MIS transistor including a shift in threshold is also suppressed. Even in the case where a floating interconnection region is present contiguously to the antenna interconnection, the provision of the interconnection for charge dissipation reduces the amount of shift in the threshold of each of the MIS transistors and equalizes the respective thresholds of the MIS transistors.

    摘要翻译： 在半导体基板的第一区域中，形成有由栅极绝缘膜，栅极电极和源极/漏极区域构成的MIS晶体管。 在半导体衬底的第二区域中，形成用作导电层的杂质扩散层。 在层间绝缘膜上形成连接到栅电极的天线布线和连接到导电层的用于电荷耗散的互连。 在用于形成互连的干蚀刻过程中，电荷通过互连进入半导体衬底以进行电荷耗散。 抑制了通过向栅电极注入电荷而导致的栅极绝缘膜的劣化，并且也抑制了包括阈值偏移的MIS晶体管的特性劣化。 即使在浮动互连区域与天线互连连续地存在的情况下，提供用于电荷耗散的互连减少了每个MIS晶体管的阈值偏移量，并且均衡了MIS晶体管的各个阈值。

    Polymeric insulating material and formed article making use of the material
    60.
    发明授权
    Polymeric insulating material and formed article making use of the material 失效
    聚合绝缘材料和使用该材料的成型制品

    公开(公告)号：US5476709A

    公开(公告)日：1995-12-19

    申请号：US73676

    申请日：1993-06-08

    申请人： Takeo Inoue ,  Shigeru Kimura ,  Tutomu Iwatani ,  Takayuki Yamada ,  Yukio Ishii ,  Ryuichi Sugimoto

    发明人： Takeo Inoue ,  Shigeru Kimura ,  Tutomu Iwatani ,  Takayuki Yamada ,  Yukio Ishii ,  Ryuichi Sugimoto

    IPC分类号： C08L23/12 ,  H01B3/44 ,  B32B7/02

    CPC分类号： C08L23/10 ,  C08L23/12 ,  H01B3/441 ,  C08L51/06 ,  C08L83/04 ,  C08L83/12 ,  Y10S428/91 ,  Y10T428/24975 ,  Y10T428/25

    摘要： The invention provides a polymeric insulating material having a high dielectric breakdown voltage. The material comprises polypropylene which has been obtained in a yield of at least 300,000 g/g-Ti based on titanium in a catalyst upon polymerization, contains ash in an amount not greater than 40 ppm by weight when analyzed by completely burning the polypropylene in air, said ash containing titanium in an amount not greater than 1 ppm by weight based on the weight of the polypropylene, and also contains chlorine in an amount not greater than 2 ppm by weight and boiling n-heptane soluble matter in an amount not smaller than 1 wt. % but not greater than 10 wt. %. According to the invention, it is possible to further improve the dielectric breakdown voltage by adding to the polypropylene an inorganic oxide or hydroxide free of particles of 10 .mu.m and greater in diameter and having an average particle size not greater than 1 .mu.m, an organopolysilane, a maleic-anhydride-grafted polypropylene, or a silane compound containing at least one organic polyether group.

    摘要翻译： 本发明提供了具有高绝缘击穿电压的聚合物绝缘材料。 该材料包括在聚合时以催化剂中钛为基准的至少300,000g / g-Ti的产率获得的聚丙烯，当通过在空气中完全燃烧聚丙烯进行分析时，含有不大于40ppm重量的灰分 所述灰分含量以聚丙烯重量计不超过1重量ppm，并且还含有不大于2重量ppm的氯和沸点正庚烷可溶物质量不小于 1重量％ ％但不大于10wt。 ％。 根据本发明，通过向聚丙烯中添加不含直径10μm以上的平均粒径为1μm以下的无机氧化物或氢氧化物，可以进一步提高介电击穿电压， 有机聚硅烷，马来酸酐接枝的聚丙烯或含有至少一个有机聚醚基团的硅烷化合物。