公开(公告)号：US20090230430A1

公开(公告)日：2009-09-17

申请号：US11921857

申请日：2006-06-12

申请人： Hironobu Miyamoto ,  Yuji Ando ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Aklo Wakejima ,  Kensuke Kasahara ,  Yasuhiro Murase ,  Kohji Matsunaga ,  Katsumi Yamanoguchi ,  Hidenori Shimawaki

发明人： Hironobu Miyamoto ,  Yuji Ando ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Aklo Wakejima ,  Kensuke Kasahara ,  Yasuhiro Murase ,  Kohji Matsunaga ,  Katsumi Yamanoguchi ,  Hidenori Shimawaki

IPC分类号： H01L29/78

CPC分类号： H01L29/404 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/802 ,  H01L29/812

摘要： A field effect transistor includes a layer structure made of compound semiconductor (111) provided on a semiconductor substrate (110) made of GaAs or InP, as an operation layer, and employs a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When, in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region, in which the second field plate electrode overlaps the upper part of a structure composed of the first field plate electrode and a gate electrode (113), is designated as Lol, and the gate length is Lg, the relation expressed as 0≦Lol/Lg≦1 holds.

摘要翻译： 场效应晶体管包括由设置在由GaAs或InP制成的半导体衬底（110）上的化合物半导体（111）作为操作层的层结构，并且采用第一场极板电极（116）和第二场极板电极 （118）。 第二场板电极包括位于第一场极板电极和漏电极（114）之间的区域中的屏蔽部分（119），用于屏蔽第一场极板电极与漏极电极。 当在栅极长度方向的截面图中，重叠区域的栅极长度方向上的长度，其中第二场极板电极与由第一场极板电极和栅电极构成的结构的上部重叠 （113）表示为Lol，栅极长度为Lg，表示为0 <= Lol / Lg <= 1的关系成立。

公开(公告)号：US20090008678A1

公开(公告)日：2009-01-08

申请号：US12279010

申请日：2007-01-29

申请人： Yuji Ando ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue

发明人： Yuji Ando ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue

IPC分类号： H01L29/778

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/201

摘要： An electron supply layer (13) is a layer which forms a heterojunction with a channel layer (12) and contains InzAlxGa1-zxN (0≦z

摘要翻译： 电子供给层（13）是与沟道层（12）形成异质结并含有In z Al x Ga 1-z x N（0 <= z <1,0 x1 / 2 <= xa <？in-line-formula description =“In-line Formulas”end =“lead”？> x1 <= 0.3。<？in-line-formula description =“In-line Formulas”end = 尾巴“？>

公开(公告)号：US06441391B1

公开(公告)日：2002-08-27

申请号：US09940374

申请日：2001-08-29

申请人： Yasuo Ohno ,  Nobuyuki Hayama ,  Kensuke Kasahara ,  Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yuji Takahashi ,  Yuji Ando ,  Kohji Matsunaga ,  Masaaki Kuzuhara

发明人： Yasuo Ohno ,  Nobuyuki Hayama ,  Kensuke Kasahara ,  Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yuji Takahashi ,  Yuji Ando ,  Kohji Matsunaga ,  Masaaki Kuzuhara

IPC分类号： H01L2906

CPC分类号： H01L29/812 ,  H01L29/045 ,  H01L29/2003

摘要： An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, heat radiation characteristic and performance in the element high speed operation; upon a sapphire substrate in which an A plane (an (11-20) plane) is set to be the basal plane, an epitaxial growth layer of a group III nitride semiconductor is formed and, thereon, a gate electrode 16, a source electrode 15 and a drain electrode 17 are formed; these electrodes are disposed in such a way that a direction along which they are laid makes an angle within 20° with respect to a C axis of sapphire.

摘要翻译： 本发明的目的是在III族氮化物半导体器件中提高元件高速运转中的生产率，散热特性和性能; 在其中A平面（（11-20）面）设置为基面的蓝宝石衬底上，形成III族氮化物半导体的外延生长层，并且在其上形成栅电极16，源电极 15和漏电极17; 这些电极被设置成使得它们被放置的方向相对于蓝宝石的C轴成20°以内的角度。

公开(公告)号：US06465814B2

公开(公告)日：2002-10-15

申请号：US09891419

申请日：2001-06-27

申请人： Kensuke Kasahara ,  Yasuo Ohno ,  Masaaki Kuzuhara ,  Hironobu Miyamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Kazuaki Kunihiro ,  Nobuyuki Hayama ,  Yuji Takahashi ,  Kouji Matsunaga

发明人： Kensuke Kasahara ,  Yasuo Ohno ,  Masaaki Kuzuhara ,  Hironobu Miyamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Kazuaki Kunihiro ,  Nobuyuki Hayama ,  Yuji Takahashi ,  Kouji Matsunaga

IPC分类号： H01L31072

CPC分类号： H01L29/7786 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/42316

摘要： A semiconductor device of the present invention comprises Al0.3Ga0.7N layer 4 and Al0.1Ga0.9N layer 5 having different Al contents as an electron supply layer on GaN layer 6 serving as an active layer. An area where Al0.3Ga0.7N layer 4 is formed is used as a low resistance area, while an area where Al0.1Ga0.9N layer 5 is formed is used as a high resistance area. As a result, a distribution of two-dimensional electrons serving as carriers is produced within a horizontal plane perpendicular to the thickness direction of the layers to form a desired device configuration. For example, when the configuration is applied to a transistor configuration, a channel concentration under a gate is reduced to improve withstand voltage between the gate and a drain, and at the same time, a channel concentration in source and drain areas is increased to realize low contact resistance.

公开(公告)号：US06440822B1

公开(公告)日：2002-08-27

申请号：US09901424

申请日：2001-07-09

申请人： Nobuyuki Hayama ,  Masaaki Kuzuhara ,  Kouji Matsunaga ,  Tatsuo Nakayama ,  Yuji Takahashi ,  Yasuo Ohno ,  Kazuaki Kunihiro ,  Kensuke Kasahara ,  Hironobu Miyamoto ,  Yuji Ando

发明人： Nobuyuki Hayama ,  Masaaki Kuzuhara ,  Kouji Matsunaga ,  Tatsuo Nakayama ,  Yuji Takahashi ,  Yasuo Ohno ,  Kazuaki Kunihiro ,  Kensuke Kasahara ,  Hironobu Miyamoto ,  Yuji Ando

IPC分类号： H01L21301

CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3677 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

摘要： In a method of manufacturing a semiconductor device, trench sections are formed on a side of one of opposing surface portions of a substrate. At lest a part of each of the trench sections is covered by a power supply metal layer which is formed on the one surface portion of the substrate. The substrate is fixed to a support such that the one surface of the substrate fits to the support. A chip is separated from the substrate using the trench sections. A conductive film is formed on side surface portions of the chip and the other surface portion of the chip. Then, the chip is separated from the support.

摘要翻译： 在制造半导体器件的方法中，沟槽部分形成在衬底的相对表面部分之一的一侧上。 每个沟槽部分的一部分由形成在基板的一个表面部分上的电源金属层覆盖。 衬底被固定到支撑件，使得衬底的一个表面适合于支撑件。 使用沟槽部分将芯片与衬底分离。 在芯片的侧表面部分和芯片的另一个表面部分上形成导电膜。 然后，芯片与支架分离。

公开(公告)号：US06765241B2

公开(公告)日：2004-07-20

申请号：US10362883

申请日：2003-02-27

申请人： Yasuo Ohno ,  Nobuyuki Hayama ,  Kensuke Kasahara ,  Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yuji Takahashi ,  Yuji Ando ,  Kohji Matsunaga ,  Masaaki Kuzuhara

发明人： Yasuo Ohno ,  Nobuyuki Hayama ,  Kensuke Kasahara ,  Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yuji Takahashi ,  Yuji Ando ,  Kohji Matsunaga ,  Masaaki Kuzuhara

IPC分类号： H01L29812

CPC分类号： H01L29/8126 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/2003

摘要： A group III nitride semiconductor device of field effect transistor type having improved productivity, reduced parasitic capacitances adapted for excellent device performance in high-speed operation as well as good heat diffusion characteristics. The device includes an epitaxial growth layer of a group III nitride semiconductor with a buffer layer laid under it, formed on an A plane (an (11-20) plane) of a sapphire. Thereon a gate electrode, a source electrode, a drain electrode, and pad electrodes are formed, and a ground conductor layer is formed on the back face of the sapphire substrate. A thickness of said sapphire substrate tsub satisfies the following Equation (1). t sub ≦ 10 ⁢ ϵ sub ⁢ S pad ϵ epi ⁢ S gate ⁢ t act where Spad is an area of the pad electrode; Sgate is an area of the gate electrode; &egr;sub is a relative permittivity of the sapphire substrate in the direction of the thickness; &egr;epi is a relative permittivity of the group III nitride semiconductor layer in the direction of the thickness; tsub is a thickness of the sapphire substrate; and tact is an effective thickness of the group III nitride semiconductor layer.

摘要翻译： 具有提高生产率的场效应晶体管类型的III族氮化物半导体器件，适于在高速操作中优异的器件性能以及良好的热扩散特性的减小的寄生电容。 该器件包括形成在蓝宝石的A平面（（11-20）面）上的具有缓冲层的III族氮化物半导体的外延生长层。 在其上形成栅电极，源电极，漏电极和焊盘电极，并且在蓝宝石衬底的背面上形成接地导体层。 所述蓝宝石衬底tsub的厚度满足以下等式（1）。其中，Spad是焊盘电极的面积; Sgate是栅电极的面积; epsilonsub是蓝宝石衬底在厚度方向上的相对介电常数;εilon 是III族氮化物半导体层在厚度方向上的相对介电常数; tsub是蓝宝石衬底的厚度; andtact是III族氮化物半导体层的有效厚度。

公开(公告)号：US06492669B2

公开(公告)日：2002-12-10

申请号：US09892567

申请日：2001-06-28

申请人： Tatsuo Nakayama ,  Yuji Ando ,  Hironobu Miyamoto ,  Kazuaki Kunihiro ,  Yuji Takahashi ,  Kensuke Kasahara ,  Nobuyuki Hayama ,  Yasuo Ohno ,  Kouji Matsunaga ,  Masaaki Kuzuhara

发明人： Tatsuo Nakayama ,  Yuji Ando ,  Hironobu Miyamoto ,  Kazuaki Kunihiro ,  Yuji Takahashi ,  Kensuke Kasahara ,  Nobuyuki Hayama ,  Yasuo Ohno ,  Kouji Matsunaga ,  Masaaki Kuzuhara

IPC分类号： H01L2980

CPC分类号： H01L29/66462 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/475 ,  H01L29/7783

摘要： A carrier travel layer is formed on the substrate of a semiconductor device with a buffer layer interposed, and a spacer layer and carrier supply layer are then formed on this carrier travel layer. On the carrier supply layer are provided a source electrode and a drain electrode, and a gate electrode is provided on an interposed Schottky layer. The carrier supply layer is composed of AlGaN and has tensile strain. The Schottky layer is composed of InGaN and has compressive strain. A negative piezoelectric charge is induced on the carrier supply layer side of the Schottky layer, and a positive piezoelectric charge is induced on the opposite side of the Schottky layer, whereby a sufficient Schottky barrier height is obtained and leakage current is suppressed.

摘要翻译： 在具有缓冲层的半导体器件的基板上形成载流子行进层，然后在该载体行进层上形成间隔层和载体供给层。 在载体供给层上设置有源电极和漏电极，在插入的肖特基层上设置有栅电极。 载体供应层由AlGaN组成并具有拉伸应变。 肖特基层由InGaN组成并具有压应变。 在肖特基层的载流子供给层侧感应出负的压电电荷，在肖特基层的相反侧产生正的压电电荷，由此获得足够的肖特基势垒高度，并且抑制泄漏电流。

公开(公告)号：US06552373B2

公开(公告)日：2003-04-22

申请号：US09818587

申请日：2001-03-28

申请人： Yuji Ando ,  Hironobu Miyamoto ,  Naotaka Iwata ,  Koji Matsunaga ,  Masaaki Kuzuhara ,  Kensuke Kasahara ,  Kazuaki Kunihiro ,  Yuji Takahashi ,  Tatsuo Nakayama ,  Nobuyuki Hayama ,  Yasuo Ohno

发明人： Yuji Ando ,  Hironobu Miyamoto ,  Naotaka Iwata ,  Koji Matsunaga ,  Masaaki Kuzuhara ,  Kensuke Kasahara ,  Kazuaki Kunihiro ,  Yuji Takahashi ,  Tatsuo Nakayama ,  Nobuyuki Hayama ,  Yasuo Ohno

IPC分类号： H01L31072

CPC分类号： H01L29/7787 ,  H01L29/2003

摘要： A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.

摘要翻译： 异质结FET在电子供给层和n型盖层之间具有包括n型杂质掺杂层的中间层。 中间层通过离子化的正电荷抵消在电子供给层和n型覆盖层之间产生的极化的负电荷，从而减少对电子的阻挡和源极/漏极电阻。

公开(公告)号：US20130069071A1

公开(公告)日：2013-03-21

申请号：US13553759

申请日：2012-07-19

申请人： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

发明人： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

IPC分类号： H01L29/778 ,  H01L29/205

CPC分类号： H01L29/778 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/432 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： Compression strains are generated at an interface between the cap layer and the barrier layer and an interface between the channel layer and the buffer layer and a tensile strain is generated at an interface between the barrier layer and the channel layer. Therefore, negative charge is higher than positive charge at the interface between the cap layer and the barrier layer and the interface between the channel layer and the buffer layer, while positive charge is higher than negative charge at the interface between the barrier layer and the channel. The channel layer has a stacked layer structure of a first layer, a second layer, and a third layer. The second layer has a higher electron affinity than those of the first layer and the third layer.

摘要翻译： 在帽层和阻挡层之间的界面处产生压缩应变，并且在沟道层和缓冲层之间的界面处产生压缩应变，并且在阻挡层和沟道层之间的界面处产生拉伸应变。 因此，负电荷高于帽层和阻挡层之间的界面处的正电荷以及沟道层与缓冲层之间的界面，而正电荷高于阻挡层和沟道之间的界面处的负电荷 。 沟道层具有第一层，第二层和第三层的堆叠层结构。 第二层比第一层和第三层具有更高的电子亲和力。

公开(公告)号：US08716755B2

公开(公告)日：2014-05-06

申请号：US13553759

申请日：2012-07-19

申请人： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

发明人： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

IPC分类号： H01L29/66

CPC分类号： H01L29/778 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/432 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： Compression strains are generated at an interface between the cap layer and the barrier layer and an interface between the channel layer and the buffer layer and a tensile strain is generated at an interface between the barrier layer and the channel layer. Therefore, negative charge is higher than positive charge at the interface between the cap layer and the barrier layer and the interface between the channel layer and the buffer layer, while positive charge is higher than negative charge at the interface between the barrier layer and the channel. The channel layer has a stacked layer structure of a first layer, a second layer, and a third layer. The second layer has a higher electron affinity than those of the first layer and the third layer.

摘要翻译： 在帽层和阻挡层之间的界面处产生压缩应变，并且在沟道层和缓冲层之间的界面处产生压缩应变，并且在阻挡层和沟道层之间的界面处产生拉伸应变。 因此，负电荷高于帽层和阻挡层之间的界面处的正电荷以及沟道层与缓冲层之间的界面，而正电荷高于阻挡层和沟道之间的界面处的负电荷 。 沟道层具有第一层，第二层和第三层的堆叠层结构。 第二层比第一层和第三层具有更高的电子亲和力。