公开(公告)号：US5453947A

公开(公告)日：1995-09-26

申请号：US12907

申请日：1993-02-03

申请人： Katsuhiro Seta ,  Hiroyuki Hara

发明人： Katsuhiro Seta ,  Hiroyuki Hara

IPC分类号： G06F12/08 ,  H01L27/10 ,  G11C15/00

CPC分类号： G06F12/0895

摘要： A tag section of a cache memory system comprises a memory for storing a plurality of first address data read out with a small amplitude (e.g., 0.2 Vpp), a circuit for comparing a plurality of second address data, input from the outside of the system, with the plurality of first address data, and providing comparison results with a second amplitude (e.g., 0.8 vpp), an OR logic circuit including a plurality of bipolar transistors having bases to which the comparison results are respectively supplied, collectors connected to a first voltage source, and emitters which are all connected to an emitter dot line, and a circuit for measuring the potential of the emitter dot line by using a reference voltage to determine that all the first and second data coincide with each other. Since a read operation with respect to each tag memory and most hit detecting operations are performed with small-amplitude signals of the ECL level, a high-speed operation can be performed.

摘要翻译： 高速缓冲存储器系统的标签部分包括用于存储以小幅度（例如，0.2Vpp）读出的多个第一地址数据的存储器，用于比较从系统外部输入的多个第二地址数据的电路 与多个第一地址数据一起提供具有第二幅度（例如，0.8vpp）的比较结果的OR逻辑电路，包括分别提供比较结果的基底的多个双极晶体管的OR逻辑电路，连接到第一 电压源和全部连接到发射体点线的发射极，以及用于通过使用参考电压来测量发射极点线的电位以确定所有第一和第二数据彼此一致的电路。 由于对于每个标签存储器的读取操作和大多数命中检测操作是以ECL电平的小振幅信号执行的，所以可以执行高速操作。

公开(公告)号：US5444654A

公开(公告)日：1995-08-22

申请号：US201091

申请日：1994-02-24

申请人： Hiroyuki Hara ,  Yoshinori Watanabe

发明人： Hiroyuki Hara ,  Yoshinori Watanabe

IPC分类号： G11C7/10 ,  G11C7/12 ,  G11C17/12 ,  H01L21/82 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/112 ,  H01L27/118 ,  G11C11/34 ,  G11C8/00

CPC分类号： H01L27/11896 ,  G11C17/12 ,  G11C7/1048 ,  G11C7/12

摘要： Disclosed is a semiconductor integrated circuit of a bipolar CMOS gate array type having a plurality of basic cells arranged in a matrix. Each cell comprises MOS transistors as memory cells, a bipolar transistor, a resistance and bit lines, for transferring data stored in the memory cells to the outside. The semiconductor integrated circuit is characterized in that the basic cells are grouped into a plurality of blocks, the bipolar NPN transistor in each block is used as a driver for reading operations of the data stored in the memory cells in each block, and the bit line is kept at a logic state "0" before the reading operations for the memory cells.

摘要翻译： 公开了具有以矩阵形式布置的多个基本单元的双极CMOS门阵列型半导体集成电路。 每个单元包括作为存储单元的MOS晶体管，双极晶体管，电阻和位线，用于将存储在存储单元中的数据传送到外部。 半导体集成电路的特征在于，将基本单元分组为多个块，每个块中的双极性NPN晶体管用作用于读取存储在每个块中的存储单元中的数据的驱动器，并且位线 在存储单元的读取操作之前保持在逻辑状态“0”。

公开(公告)号：US5365124A

公开(公告)日：1994-11-15

申请号：US095764

申请日：1993-07-23

申请人： Katsuhiro Seta ,  Hiroyuki Hara

发明人： Katsuhiro Seta ,  Hiroyuki Hara

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H03K17/567 ,  H03K19/013 ,  H03K19/0175 ,  H03K19/08 ,  H03K19/0944

CPC分类号： H03K19/0136 ,  H03K19/09448

摘要： An input terminal IN is connected to the input of a CMOS inverter, and also to the gate of an N-channel MOS transistor N10. The output of the CMOS inverter is coupled to the base of an NPN transistor Q11 used for pulling up the output terminal OUT. The drain of the transistor N10 is connected to the input of a CMOS inverter. The output of the inverter is connected to the base of an NPN transistor Q12 used for pulling down the output terminal OUT. The emitter of the transistor Q11 and the collector of the transistor Q12 are connected to an output terminal OUT, which is coupled to the gate of a P-channel MOS transistor P12 and the gate of an N-channel MOS transistor N3. The drain of the transistor P12 is connected to the drain of the transistor N10. The drain of the transistor N13 is connected to the source of the transistor N10. The transistors N10, P12, and N13 constitute a circuit for controlling the CMOS inverter.

摘要翻译： 输入端子IN连接到CMOS反相器的输入端，并且连接到N沟道MOS晶体管N10的栅极。 CMOS反相器的输出耦合到用于提升输出端OUT的NPN晶体管Q11的基极。 晶体管N10的漏极连接到CMOS反相器的输入端。 反相器的输出端连接到用于拉出输出端子OUT的NPN晶体管Q12的基极。 晶体管Q11的发射极和晶体管Q12的集电极连接到耦合到P沟道MOS晶体管P12的栅极和N沟道MOS晶体管N3的栅极的输出端子OUT。 晶体管P12的漏极连接到晶体管N10的漏极。 晶体管N13的漏极连接到晶体管N10的源极。 晶体管N10，P12和N13构成用于控制CMOS反相器的电路。

公开(公告)号：US5126595A

公开(公告)日：1992-06-30

申请号：US689707

申请日：1991-04-19

申请人： Hiroyuki Hara ,  Yasuhiro Sugimoto

发明人： Hiroyuki Hara ,  Yasuhiro Sugimoto

IPC分类号： H01L27/06 ,  H01L21/8249 ,  H03K17/567 ,  H03K19/013 ,  H03K19/08 ,  H03K19/0944

CPC分类号： H03K19/09448 ,  H03K19/013

摘要： A P-channel MOSFET includes a gate for receiving an input signal, a source connected to a power supply terminal to which a high power supply voltage is applied, and a drain connected to the base of an NPN bipolar transistor at an output stage. The collector of the bipolar transistor is connected to the power supply terminal and the emitter thereof is connected to an output terminal. An N-channel MOSFET includes a gate for receiving the input signal, a drain connected to the output terminal, and a source and a back gate both connected to the base of an NPN bipolar transistor at the output stage. The collector of the bipolar transistor is connected to the output terminal, and the emitter thereof is connected to a power supply terminal to which a power supply voltage of ground potential is applied.

公开(公告)号：US5066996A

公开(公告)日：1991-11-19

申请号：US684513

申请日：1991-04-15

申请人： Hiroyuki Hara ,  Yasuhiro Sugimoto ,  Tetsu Nagamatsu

发明人： Hiroyuki Hara ,  Yasuhiro Sugimoto ,  Tetsu Nagamatsu

IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/08 ,  H01L27/118 ,  H03K19/0944 ,  H03K19/173

CPC分类号： H03K19/09448 ,  H01L27/11896 ,  H03K19/1735

摘要： A semiconductor device is disclosed having a channelless gate array. A plurality of standard cells are formed on a gate array chip such that one of the standard cells is formed relative to the adjacent standard cell with a bipolar transistor and resistor shared, as a BiCMOS logic gate, by the mutually adjacent standard cells at one end.

公开(公告)号：US5039884A

公开(公告)日：1991-08-13

申请号：US511748

申请日：1990-04-20

申请人： Hiroyuki Hara

发明人： Hiroyuki Hara

IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118

CPC分类号： H01L27/11898

摘要： A gate array semiconductor integrated circuit includes a plurality of input/output cells, an input/output circuit, and a bias circuit. The plurality of input/output cells are arranged around an internal logic gate. The input/output circuit is formed by an aluminum master slice of the input/output cells and performs an input/output operation for the internal logic gate. The bias circuit is formed by the aluminum master slice of the input/output cells to supply a predetermined bias voltage to the input/output circuit.

公开(公告)号：US4740907A

公开(公告)日：1988-04-26

申请号：US716090

申请日：1985-03-26

申请人： Shoichi Shimizu ,  Yukio Kamatani ,  Yasuhiro Sugimoto ,  Hiroyuki Hara

发明人： Shoichi Shimizu ,  Yukio Kamatani ,  Yasuhiro Sugimoto ,  Hiroyuki Hara

IPC分类号： G06F7/501 ,  G06F7/50 ,  G06F7/503

CPC分类号： G06F7/5016 ,  G06F7/501 ,  G06F2207/4806

摘要： A high-speed full adder circuit comprising a plurality of differential transistor pairs and operating at multiple logic levels. This full adder can be made up of basic logic circuits, each having differential transistor pairs, such as exclusive-OR circuits, AND circuits and OR circuits. To reduce the chip size of the full adder, while ensuring a high-speed operation, transistors which may be used in common are replaced by a smaller number of transistors, thereby reducing the number of required transistors.

摘要翻译： 一种包括多个差分晶体管对并以多个逻辑电平工作的高速全加器电路。 这个全加器可以由各自具有差分晶体管对的基本逻辑电路组成，例如异或电路，AND电路和OR电路。 为了减小全加器的芯片尺寸，在确保高速运行的同时，可以共同使用的晶体管被​​更少数量的晶体管代替，从而减少所需晶体管的数量。

公开(公告)号：US4695750A

公开(公告)日：1987-09-22

申请号：US770090

申请日：1985-08-28

申请人： Hiroyuki Hara ,  Michinori Nakamura ,  Yasuhiro Sugimoto

发明人： Hiroyuki Hara ,  Michinori Nakamura ,  Yasuhiro Sugimoto

IPC分类号： H03K19/017 ,  H03K19/0175 ,  H03K19/092 ,  H03K17/10 ,  H03K19/003 ,  H03K19/086

CPC分类号： H03K19/017527 ,  H03K19/01707

摘要： A voltage level converting circuit includes first and second potential terminals between which a power source voltage is applied, first and second terminals for receiving an input signal and an inverted input signal, a differential amplifier including npn transistors whose conduction states are controlled by the input signal and the inverted input signal, and an output circuit for generating an output logic signal corresponding to the output voltage of the differential amplifier. The output circuit of this voltage level converting circuit has a current path connected in series between the first and second potential terminals by way of a constant current source, and includes a MOS transistor whose conduction state is controlled by the output voltage of the differential amplifier.

摘要翻译： 电压电平转换电路包括施加电源电压的第一和第二电位端子，用于接收输入信号的第一和第二端子和反相输入信号，包括npn晶体管的差分放大器，其导通状态由输入信号 和反相输入信号，以及用于产生与差分放大器的输出电压对应的输出逻辑信号的输出电路。 该电压电平转换电路的输出电路具有通过恒流源串联连接在第一和第二电位端子之间的电流路径，并且包括MOS晶体管，其导通状态由差分放大器的输出电压控制。

公开(公告)号：US08861013B2

公开(公告)日：2014-10-14

申请号：US14076221

申请日：2013-11-10

申请人： Hiroyuki Hara

发明人： Hiroyuki Hara

IPC分类号： G06K15/00 ,  G06K15/02

CPC分类号： G06K15/181 ,  G06F3/1297 ,  G06K15/00 ,  G06K15/02 ,  G06K15/1827 ,  G06K15/1851 ,  G06K15/1857 ,  G06K15/1863 ,  H04N2201/0082

摘要： A CPU perform the steps of: (a) causing a compression/decompression processor to decompress the compressed data of one of three bands in the data area except for the first block in the band, and storing decompressed bitmap data in the data area; (b) rasterizing each of the intermediate data blocks in the band and synthesizing the rasterized data and the decompressed bitmap data in the band; and (c) causing the compression/decompression processor to compress the synthesized bitmap data and storing the compressed data in the data area. The CPU performs the steps (a) to (c) in different respective tasks in parallel, and performs the steps (a) to (c) along the order of (a), (b), (c) for each of the intermediate code blocks in each of the bands while using the 1st to the 3rd bitmap data area in turn for each of the steps (a) to (c).

摘要翻译： CPU执行以下步骤：（a）使压缩/解压缩处理器解压缩除频带中的第一块以外的数据区域中的三个频带之一的压缩数据，并将解压缩的位图数据存储在数据区域中; （b）对频带中的每个中间数据块进行光栅化，并合成光栅化数据和频带中的解压缩位图数据; 和（c）使压缩/解压缩处理器压缩合成位图数据并将压缩数据存储在数据区中。 CPU在不同的各个任务中并行执行步骤（a）至（c），并且按照（a），（b），（c）的顺序对于每个中间体执行步骤（a）至（c） 对于每个步骤（a）至（c）中的每一个依次使用第一至第三位图数据区域，每个频带中的代码块。

公开(公告)号：US08643814B2

公开(公告)日：2014-02-04

申请号：US13429510

申请日：2012-03-26

申请人： Tomoki Yokota ,  Hiroyuki Hara

发明人： Tomoki Yokota ,  Hiroyuki Hara

IPC分类号： G02F1/1343

CPC分类号： G02F1/133345 ,  G02F2001/133388 ,  G02F2201/501 ,  G09G3/002 ,  G09G3/3648 ,  G09G2300/0417 ,  G09G2310/0232 ,  G09G2320/043

摘要： In at least one embodiment of the disclosure, a liquid crystal device comprises a plurality of conductive patterns formed of a conductive film in a peripheral region between an image display region and a sealing member. The conductive patterns are formed at a same layer as a plurality of pixel electrodes. An insulation film is formed on a side facing a counter substrate so as to correspond to the plurality of conductive patterns and a plurality of pixel electrodes. Peripheral electrodes are formed in a region overlapping the plurality of conductive patterns in a plan view on a side on which the counter substrate is located so as to correspond to the insulation film in the peripheral region.

摘要翻译： 在本公开的至少一个实施例中，液晶装置包括由图像显示区域和密封构件之间的周边区域中的导电膜形成的多个导电图案。 导电图案形成在与多个像素电极相同的层上。 在对向基板的一侧形成绝缘膜，以对应于多个导电图案和多个像素电极。 外周电极形成在与对置基板的一侧的平面图中与多个导电图案重叠的区域中，以与周边区域中的绝缘膜相对应。