公开(公告)号：US5258957A

公开(公告)日：1993-11-02

申请号：US849458

申请日：1992-03-11

申请人： Katsuhiro Seta ,  Hiroyuki Hara ,  Takayasu Sakurai ,  Yoshinori Watanabe

发明人： Katsuhiro Seta ,  Hiroyuki Hara ,  Takayasu Sakurai ,  Yoshinori Watanabe

IPC分类号： G11C11/41 ,  G11C7/06 ,  G11C7/18 ,  G11C11/401 ,  G11C11/414 ,  G11C13/00

CPC分类号： G11C7/062 ,  G11C7/18

摘要： In a semiconductor memory device of a divided bit line system, read signals from memory cell blocks are sense-amplified together by a single differential bit line sense amplifier. The bit line sense amplifier includes a plurality of first transistors, the base electrodes of which are connected to local bit lines of the memory cell blocks, the emitter electrodes of which are commonly connected to corresponding main bit lines, and the collector electrodes of which are connected to a first power supply node, a second transistor, which forms a differential pair with each of the first transistors, the base electrode of which is applied with a reference bias potential, and the emitter electrode of which is connected to the main bit lines, a current source connected between the emitter electrode of the second transistor, and a second power supply node, and a load circuit connected between the collector electrode of the second transistor and the first power supply node. The main bit lines with a heavy load can be driven by the emitters having a large driving force, and the outputs from the memory cell blocks can be sensed without going through selectors, thus attaining high-speed read access.

公开(公告)号：US5444654A

公开(公告)日：1995-08-22

申请号：US201091

申请日：1994-02-24

申请人： Hiroyuki Hara ,  Yoshinori Watanabe

发明人： Hiroyuki Hara ,  Yoshinori Watanabe

IPC分类号： G11C7/10 ,  G11C7/12 ,  G11C17/12 ,  H01L21/82 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/112 ,  H01L27/118 ,  G11C11/34 ,  G11C8/00

CPC分类号： H01L27/11896 ,  G11C17/12 ,  G11C7/1048 ,  G11C7/12

摘要： Disclosed is a semiconductor integrated circuit of a bipolar CMOS gate array type having a plurality of basic cells arranged in a matrix. Each cell comprises MOS transistors as memory cells, a bipolar transistor, a resistance and bit lines, for transferring data stored in the memory cells to the outside. The semiconductor integrated circuit is characterized in that the basic cells are grouped into a plurality of blocks, the bipolar NPN transistor in each block is used as a driver for reading operations of the data stored in the memory cells in each block, and the bit line is kept at a logic state "0" before the reading operations for the memory cells.

摘要翻译： 公开了具有以矩阵形式布置的多个基本单元的双极CMOS门阵列型半导体集成电路。 每个单元包括作为存储单元的MOS晶体管，双极晶体管，电阻和位线，用于将存储在存储单元中的数据传送到外部。 半导体集成电路的特征在于，将基本单元分组为多个块，每个块中的双极性NPN晶体管用作用于读取存储在每个块中的存储单元中的数据的驱动器，并且位线 在存储单元的读取操作之前保持在逻辑状态“0”。

公开(公告)号：US5289405A

公开(公告)日：1994-02-22

申请号：US661020

申请日：1991-02-26

申请人： Hiroyuki Hara ,  Yoshinori Watanabe

发明人： Hiroyuki Hara ,  Yoshinori Watanabe

IPC分类号： H01L27/118 ,  G11C7/06 ,  G11C8/16 ,  G11C11/419 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C8/16 ,  G11C11/419 ,  G11C7/067

摘要： A semiconductor memory circuit device having memory cells constructed on a BiCMOS gate array includes amplifying means constituted by a bipolar transistor connected to the output stage of each of memory cells arranged in a matrix form on a semiconductor substrate and formed in a gate array memory cell configuration by use of the Master slice approach. The amplifying means amplifies the potential level of readout data of the memory cell and output the same to an output line, thus enhancing the driving ability of the output line and reducing the whole readout time for reading out data from the memory circuit.

摘要翻译： 具有构造在BiCMOS门阵列上的存储单元的半导体存储器电路器件包括由半导体衬底上以矩阵形式布置的每个存储单元的输出级连接的双极型晶体管构成的放大装置，形成为栅阵列存储单元配置 通过使用主切片方法。 放大装置放大存储单元的读出数据的电位并将其输出到输出线，从而提高输出线的驱动能力，并减少用于从存储器电路读出数据的整个读出时间。

公开(公告)号：US08873126B2

公开(公告)日：2014-10-28

申请号：US13550815

申请日：2012-07-17

申请人： Naoki Tomikawa ,  Hiroyuki Hara ,  Tomoki Yokota

发明人： Naoki Tomikawa ,  Hiroyuki Hara ,  Tomoki Yokota

IPC分类号： G02F1/03 ,  G02F1/07 ,  G02F1/29 ,  H01H3/00

CPC分类号： G02F1/03 ,  G02F1/134309 ,  G02F2001/133388 ,  G02F2201/124

摘要： An electrooptic device includes first and second substrates that are disposed opposing each other with an electrooptic material layer therebetween, a sealing material that bonds the first and second substrates, a pixel area, and an ion trap portion between the pixel area and the sealing material. The ion trap portion includes first and second electrodes that are formed in a comb-tooth shape and are disposed so that branch electrodes of the first electrode and branch electrodes of the second electrode are engaged with each other. A direction of the branch electrodes intersects with an orientation direction of the electrooptic material at an interface between the electrooptic material layer and the first substrate.

摘要翻译： 电光装置包括彼此相对设置的第一和第二基板，其间具有电光材料层，在像素区域和密封材料之间结合第一和​​第二基板，像素区域和离子捕获部分的密封材料。 离子捕获部包括形成为梳齿形状的第一电极和第二电极，并且被配置为使得第一电极的分支电极和第二电极的分支电极彼此接合。 分支电极的方向在电光材料层和第一基板之间的界面处与电光材料的取向方向相交。

公开(公告)号：US20140063554A1

公开(公告)日：2014-03-06

申请号：US14076221

申请日：2013-11-10

申请人： Hiroyuki Hara

发明人： Hiroyuki Hara

IPC分类号： G06K15/02

CPC分类号： G06K15/181 ,  G06F3/1297 ,  G06K15/00 ,  G06K15/02 ,  G06K15/1827 ,  G06K15/1851 ,  G06K15/1857 ,  G06K15/1863 ,  H04N2201/0082

摘要： A CPU perform the steps of: (a) causing a compression/decompression processor to decompress the compressed data of one of three bands in the data area except for the first block in the band, and storing decompressed bitmap data in the data area; (b) rasterizing each of the intermediate data blocks in the band and synthesizing the rasterized data and the decompressed bitmap data in the band; and (c) causing the compression/decompression processor to compress the synthesized bitmap data and storing the compressed data in the data area. The CPU performs the steps (a) to (c) in different respective tasks in parallel, and performs the steps (a) to (c) along the order of (a), (b), (c) for each of the intermediate code blocks in each of the bands while using the 1st to the 3rd bitmap data area in turn for each of the steps (a) to (c).

摘要翻译： CPU执行以下步骤：（a）使压缩/解压缩处理器解压缩除频带中的第一块以外的数据区域中的三个频带之一的压缩数据，并将解压缩的位图数据存储在数据区域中; （b）对频带中的每个中间数据块进行光栅化，并合成光栅化数据和频带中的解压缩位图数据; 和（c）使压缩/解压缩处理器压缩合成位图数据并将压缩数据存储在数据区中。 CPU在不同的各个任务中并行执行步骤（a）至（c），并且按照（a），（b），（c）的顺序对于每个中间体执行步骤（a）至（c） 对于每个步骤（a）至（c）中的每一个依次使用第一至第三位图数据区域，每个频带中的代码块。

公开(公告)号：US20140063529A1

公开(公告)日：2014-03-06

申请号：US14076217

申请日：2013-11-10

申请人： Hiroyuki Hara

发明人： Hiroyuki Hara

IPC分类号： G06K15/02

CPC分类号： G06K15/181 ,  G06F3/1297 ,  G06K15/00 ,  G06K15/02 ,  G06K15/1827 ,  G06K15/1851 ,  G06K15/1857 ,  G06K15/1863 ,  H04N2201/0082

摘要： A CPU perform the steps of: (a) causing a compression/decompression processor to decompress the compressed data of one of three bands in the data area except for the first block in the band, and storing decompressed bitmap data in the data area; (b) rasterizing each of the intermediate data blocks in the band and synthesizing the rasterized data and the decompressed bitmap data in the band; and (c) causing the compression/decompression processor to compress the synthesized bitmap data and storing the compressed data in the data area. The CPU performs the steps (a) to (c) in different respective tasks in parallel, and performs the steps (a) to (c) along the order of (a), (b), (c) for each of the intermediate code blocks in each of the bands while using the 1st to the 3rd bitmap data area in turn for each of the steps (a) to (c).

公开(公告)号：US08661209B2

公开(公告)日：2014-02-25

申请号：US13048296

申请日：2011-03-15

申请人： Hiroyuki Hara

发明人： Hiroyuki Hara

IPC分类号： G06F12/00 ,  G06F3/12 ,  G06K15/02 ,  G06F15/02

CPC分类号： G06F3/12 ,  G06F12/00 ,  G06F15/0283 ,  G06K15/02 ,  H04N1/32561 ,  H04N1/32587

摘要： A data processing apparatus includes a storage controller and a processor. The storage controller is configured to write a series of data blocks constituting a particular unit of data to a storage and read out the series of data blocks from the storage. The processor is further configured to generate a write-side process and a read-side process, notify the read-side process from the write-side process of an identifier of a storage area in the storage, cause the storage controller to sequentially write the series of data blocks to the storage area using the write-side process, and cause the storage controller to read the series of data blocks from the storage area corresponding to the identifier using the read-side process after the identifier is received in the read-side process.

摘要翻译： 数据处理装置包括存储控制器和处理器。 存储控制器被配置为将构成特定数据单元的一系列数据块写入存储器并从存储器读出一系列数据块。 处理器还被配置为生成写入侧处理和读取侧处理，从写入侧处理向存储器中的存储区域的标识符通知读取侧处理，使存储控制器顺序地写入 一系列数据块使用写入侧处理存储到存储区域，并且使存储控制器在读取侧处理中接收到标识符之后，使用读取侧处理从与标识符对应的存储区域读取一系列数据块。 边过程。

公开(公告)号：US20120099067A1

公开(公告)日：2012-04-26

申请号：US13269689

申请日：2011-10-10

申请人： Hiroyuki Hara ,  Tomoki Yokota

发明人： Hiroyuki Hara ,  Tomoki Yokota

IPC分类号： G02F1/1343

CPC分类号： G02F1/136277 ,  G02F1/13454 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/133388 ,  G02F2001/13456 ,  G02F2001/13629 ,  G02F2201/48 ,  H04N9/3105

摘要： In a display region, pixel electrodes are arranged with a predetermined pitch in a matrix. Dummy pixel electrodes provided in a dummy display region surrounding the display region are formed from the same layer as the pixel electrodes, and are arranged in an island shape so as to have the same size and pitch as the pixel electrodes. The dummy pixel electrodes are connected to each other via a wire positioned under the pixel electrodes.

摘要翻译： 在显示区域中，像素电极以矩阵形式以预定间距排列。 设置在显示区域周围的虚拟显示区域中的虚拟像素电极由与像素电极相同的层形成，并且以与像素电极相同的尺寸和间距排列成岛状。 虚拟像素电极通过位于像素电极下方的布线彼此连接。

公开(公告)号：US20120062535A1

公开(公告)日：2012-03-15

申请号：US13321761

申请日：2010-03-11

申请人： Hiroyuki Hara

发明人： Hiroyuki Hara

IPC分类号： G06F3/038

CPC分类号： G09G3/3614 ,  G02F2001/133397 ,  G02F2203/30 ,  G09G3/2022 ,  G09G3/3648

摘要： In an electro-optical device, a liquid crystal element can be driven more appropriately.An electro-optical device 1 includes: a scanning line driving circuit 130 which, in a plurality of subfields sf1 to sf8 constituting a field, sequentially supplies scanning signals for causing selection transistors 116 to be in an ON state to a plurality of scanning lines 112 and selects a pixel 110 for each of the scanning lines 112; and a data line driving circuit 140 which writes a signal potential corresponding to an image to be displayed on a pixel electrode 118 of the pixel 110 selected by the scanning line driving circuit 130 via a plurality of data lines 114, in the writing of the signal potential, when it is assumed that a polarity of the signal potential with respect to a potential of an opposite electrode 119 is a writing polarity, reverses the writing polarity a plurality of times in the field, and writes the signal potential so that the writing polarities of the plurality of subfield periods constituting a given field are the reverse of the writing polarities of the plurality of subfields constituting the next field.

摘要翻译： 在电光装置中，可以更合适地驱动液晶元件。 电光装置1包括：扫描线驱动电路130，其在构成场的多个子场sf1〜sf8中顺序地向多条扫描线112供给使选择晶体管116处于导通状态的扫描信号 并为每个扫描线112选择像素110; 以及数据线驱动电路140，通过多条数据线114，将由扫描线驱动电路130选择的像素110的像素电极118上的要显示的图像的信号电位写入信号 当假设相对于相对电极119的电位的信号电位的极性是写入极性时，在场中反复写入极性多次，并且写入信号电位，使得写入极性 构成给定场的多个子场周期与构成下一场的多个子场的写入极性相反。

公开(公告)号：US20070268347A1

公开(公告)日：2007-11-22

申请号：US11750152

申请日：2007-05-17

申请人： Kazuhiko Amano ,  Naoyuki Toyoda ,  Hiroyuki Hara ,  Takayuki Kondo

发明人： Kazuhiko Amano ,  Naoyuki Toyoda ,  Hiroyuki Hara ,  Takayuki Kondo

IPC分类号： B41J2/175

CPC分类号： B41J2/17523 ,  B41J2/175 ,  B41J2/17513 ,  B41J2/1752 ,  B41J2/1753 ,  B41J2/17553 ,  B41J2/17566

摘要： An ink cartridge that is filled with ink and, used with the ink cartridge loaded into a printer includes a reservoir that reserves the ink, an outlet through which the ink is supplied to the printer with the ink cartridge loaded, at least one ink supply system that includes a channel that leads the ink from the reservoir to the outlet, and a sensor that detects whether the channel is filled with the ink or gas, an ink cartridge terminal that is electrically coupled to the sensor and makes contact with a printer terminal disposed on the printer upon loading of the ink cartridge. A detection region of the channel where detection is carried out by the sensor is previously filled with gas with the ink cartridge yet to be used. Whether or not the use of the ink cartridge is proper is determined based on information from the sensor.

摘要翻译： 填充有墨水的墨盒和与装入打印机的墨盒一起使用的墨盒包括储存墨水的储存器，在墨水盒装载的情况下将墨水供应到打印机的出口，至少一个墨水供应系统 其包括将墨水从储存器引导到出口的通道，以及检测通道是否填充有墨水或气体的传感器，电耦合到传感器并与布置的打印机端子接触的墨盒端子 在打印机上装入墨盒时。 通过传感器进行检测的通道的检测区域预先用未被使用的墨盒填充气体。 基于来自传感器的信息来确定墨盒的使用是否合适。