公开(公告)号：US20170103896A1

公开(公告)日：2017-04-13

申请号：US15243986

申请日：2016-08-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Chih-Sen Huang ,  Chun-Hsien Lin

IPC: H01L21/28 ,  H01L21/285 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/28123 ,  H01L21/28088 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0653 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of : providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.

公开(公告)号：US09613969B2

公开(公告)日：2017-04-04

申请号：US14793714

申请日：2015-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Wei-Cyuan Lo ,  Ming-Jui Chen ,  Chia-Lin Lu ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Tan-Ya Yin ,  Chia-Wei Huang ,  Shu-Ru Wang ,  Yung-Feng Cheng

IPC: H01L27/11 ,  H01L29/76 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L21/823871 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/7851 ,  H01L29/7853

Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.

公开(公告)号：US09564371B2

公开(公告)日：2017-02-07

申请号：US14514374

申请日：2014-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Tsung-Hung Chang ,  Jia-Rong Wu ,  Ching-Ling Lin ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/823475 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823431

Abstract: A manufacturing method for forming a semiconductor device includes: first, a substrate is provided, a fin structure is formed on the substrate, and a plurality of gate structures are formed on the fin structure, next, a hard mask layer and a first photoresist layer are formed on the fin structure, an first etching process is then performed on the first photoresist layer, afterwards, a plurality of patterned photoresist layers are formed on the remaining first photoresist layer and the remaining hard mask layer, where each patterned photoresist layer is disposed right above each gate structure, and the width of each patterned photoresist is larger than the width of each gate structure, and the patterned photoresist layer is used as a hard mask to perform an second etching process to form a plurality of second trenches.

Abstract translation: 一种半导体器件的制造方法，其特征在于，首先，在基板上形成有基板，在所述散热片结构上形成有多个栅极结构，然后将硬掩模层和第一光致抗蚀剂层 形成在鳍结构上，然后在第一光致抗蚀剂层上进行第一蚀刻工艺，然后在剩余的第一光致抗蚀剂层和剩余的硬掩模层上形成多个图案化的光致抗蚀剂层，其中每个图案化的光致抗蚀剂层被设置 每个栅极结构的正上方，并且每个图案化的光致抗蚀剂的宽度大于每个栅极结构的宽度，并且图案化的光致抗蚀剂层用作硬掩模以执行第二蚀刻工艺以形成多个第二沟槽。

公开(公告)号：US20160351575A1

公开(公告)日：2016-12-01

申请号：US14793714

申请日：2015-07-07

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Wei-Cyuan Lo ,  Ming-Jui Chen ,  Chia-Lin Lu ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Tan-Ya Yin ,  Chia-Wei Huang ,  Shu-Ru Wang ,  Yung-Feng Cheng

IPC: H01L27/11 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L21/823871 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/7851 ,  H01L29/7853

Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.

Abstract translation: 本发明提供一种半导体结构，其包括基板，多个翅片结构，多个栅极结构，电介质层和多个接触插塞。 衬底具有存储区域。 翅片结构设置在存储区域中的基板上，每个沿着第一方向延伸。 栅极结构设置在翅片结构上，每个翼结构沿着第二方向延伸。 电介质层设置在栅极结构和鳍结构上。 接触插头设置在电介质层中并电连接到鳍结构中的源极/漏极区域。 从顶部看，接触塞具有梯形或五边形。 本发明还提供了一种形成该方法的方法。

公开(公告)号：US20160064327A1

公开(公告)日：2016-03-03

申请号：US14494607

申请日：2014-09-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Yi-Wei Chen

IPC: H01L23/535 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/53261 ,  H01L23/53266 ,  H01L27/0629

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first metal gate on the substrate; a first hard mask on the first metal gate; an interlayer dielectric (ILD) layer on top of and around the first metal gate; and a patterned metal layer embedded in the ILD layer, in which the top surface of the patterned metal layer is lower than the top surface of the first hard mask.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：衬底; 基板上的第一金属栅极; 第一个金属门上的第一个硬掩模; 在第一金属栅极的顶部和周围的层间绝缘层（ILD）层; 以及嵌入ILD层中的图案化金属层，其中图案化金属层的顶表面比第一硬掩模的顶表面低。

公开(公告)号：US09117886B2

公开(公告)日：2015-08-25

申请号：US14091349

申请日：2013-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Jia-Rong Wu ,  Ching-Wen Hung

IPC: H01L21/338 ,  H01L21/44 ,  H01L21/768 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/7827 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for fabricating a semiconductor device is provided according to one embodiment of the present invention and includes forming an interlayer dielectric on a substrate; forming a trench surrounded by the interlayer dielectric; depositing a dielectric layer and a work function layer on a surface of the trench sequentially and conformally; filling up the trench with a conductive layer; removing an upper portion of the conductive layer inside the trench; forming a protection film on a top surface of the interlayer dielectric and a top surface of the conductive layer through a directional deposition process; removing the dielectric layer exposed from the protection film; and forming a hard mask to cover the protection film.

Abstract translation: 根据本发明的一个实施例提供一种制造半导体器件的方法，包括在衬底上形成层间电介质; 形成由层间电介质包围的沟槽; 依次和保形地在沟槽的表面上沉积介电层和功函数层; 用导电层填充沟槽; 去除沟槽内的导电层的上部; 通过定向沉积工艺在层间电介质的顶表面和导电层的顶表面上形成保护膜; 去除从保护膜暴露的电介质层; 并形成硬掩模以覆盖保护膜。

公开(公告)号：US20150145027A1

公开(公告)日：2015-05-28

申请号：US14091349

申请日：2013-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Jia-Rong Wu ,  Ching-Wen Hung

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for fabricating a semiconductor device is provided according to one embodiment of the present invention and includes forming an interlayer dielectric on a substrate; forming a trench surrounded by the interlayer dielectric; depositing a dielectric layer and a work function layer on a surface of the trench sequentially and conformally; filling up the trench with a conductive layer; removing an upper portion of the conductive layer inside the trench; forming a protection film on a top surface of the interlayer dielectric and a top surface of the conductive layer through a directional deposition process; removing the dielectric layer exposed from the protection film; and forming a hard mask to cover the protection film.

Abstract translation: 根据本发明的一个实施例提供一种制造半导体器件的方法，包括在衬底上形成层间电介质; 形成由层间电介质包围的沟槽; 依次和保形地在沟槽的表面上沉积介电层和功函数层; 用导电层填充沟槽; 去除沟槽内的导电层的上部; 通过定向沉积工艺在层间电介质的顶表面和导电层的顶表面上形成保护膜; 去除从保护膜暴露的电介质层; 并形成硬掩模以覆盖保护膜。

公开(公告)号：US09006110B1

公开(公告)日：2015-04-14

申请号：US14074720

申请日：2013-11-08

Applicant: United Microelectronics Corp.

Inventor： Chien-Ying Sun ,  En-Chiuan Liou ,  Jia-Rong Wu ,  Ching-Wen Hung

IPC: H01L21/311 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/308

CPC classification number: H01L21/30604 ,  H01L21/3083 ,  H01L21/823431

Abstract: A method for fabricating a patterned structure of a semiconductor device includes: forming first mandrels and second mandrels on a substrate, wherein a first spacing is defined between the two adjacent first mandrels and a second spacing is defined between the two adjacent second mandrels, the first spacing being wider than the second spacing; forming a cover layer to cover the first mandrels while exposing the second mandrels; etching the cover layer and the second mandrels; removing the cover layer; concurrently forming first spacers on the sides of the first mandrels and a second spacers on the sides of the second mandrels after removing the cover layer; and transferring a layout of the first and second spacers to the substrate so as to form fin-shaped structures.

Abstract translation: 一种用于制造半导体器件的图案化结构的方法包括：在衬底上形成第一心轴和第二心轴，其中在所述两个相邻的第一心轴之间限定第一间隔，并且在所述两个相邻的第二心轴之间限定第二间距， 间隔宽于第二间距; 形成覆盖层以覆盖所述第一心轴同时暴露所述第二心轴; 蚀刻覆盖层和第二芯棒; 去除覆盖层; 在去除覆盖层之后，同时在第一心轴的侧面上形成第一间隔物和在第二心轴的侧面上的第二间隔物; 以及将所述第一和第二间隔物的布局转移到所述基底以形成鳍状结构。

公开(公告)号：US08962490B1

公开(公告)日：2015-02-24

申请号：US14048043

申请日：2013-10-08

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Chih-Sen Huang ,  Chieh-Te Chen

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/76802 ,  H01L29/66477

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon, wherein at least one metal gate is formed in the ILD layer and at least one source/drain region is adjacent to two sides of the metal gate; forming a first dielectric layer on the ILD layer; forming a second dielectric layer on the first dielectric layer; performing a first etching process to partially remove the second dielectric layer; utilizing a first cleaning agent for performing a first wet clean process; performing a second etching process to partially remove the first dielectric layer; and utilizing a second cleaning agent for performing a second wet clean process, wherein the first cleaning agent is different from the second cleaning agent.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底，其中至少一个金属栅极形成在ILD层中，并且至少一个源极/漏极区域邻近金属栅极的两侧; 在ILD层上形成第一介电层; 在所述第一电介质层上形成第二电介质层; 执行第一蚀刻工艺以部分地去除所述第二介电层; 利用第一清洁剂进行第一次湿清洁处理; 执行第二蚀刻工艺以部分地去除所述第一介电层; 并且利用第二清洁剂进行第二湿式清洁处理，其中所述第一清洁剂与所述第二清洁剂不同。

公开(公告)号：US20140191358A1

公开(公告)日：2014-07-10

申请号：US13736082

申请日：2013-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Jia-Rong Wu

IPC: H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76235 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure comprises an upper insulating portion and a lower insulating portion, wherein the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. A part of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled.

Abstract translation: 提供浅沟槽隔离（STI）及其形成方法。 STI结构包括上绝缘部分和下绝缘部分，其中下绝缘部分包括第一绝缘体和围绕第一绝缘体的绝缘层，上绝缘部分包括第二绝缘体和围绕第二绝缘体的缓冲层。 缓冲层的一部分在第一绝缘体和第二绝缘体之间接合，缓冲层的外侧壁和第一绝缘体的侧壁平整。