公开(公告)号：US10925172B1

公开(公告)日：2021-02-16

申请号：US16702478

申请日：2019-12-03

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Tse-Wei Wang

IPC: H05K3/46 ,  H05K1/11 ,  H05K3/40 ,  H05K1/03

Abstract: A carrier structure includes a carrier having at least one through hole penetrating the carrier and a build-up circuit layer located on the carrier and including at least one first circuit layer, at least one first dielectric layer, a second circuit layer, a second dielectric layer, and a plurality of conductive vias. The first circuit layer is located on a first surface of the carrier and includes at least one first pad disposed relative to the through hole. The first dielectric layer is located on the first circuit layer. The second circuit layer is located on the first dielectric layer and includes at least one second pad. The second dielectric layer is located on the second circuit layer and includes at least one opening exposing the second pad. The conductive vias penetrate the first dielectric layer and are electrically connected to the first and second circuit layers.

公开(公告)号：US10685922B2

公开(公告)日：2020-06-16

申请号：US16240806

申请日：2019-01-07

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Cheng-Ta Ko ,  Yu-Hua Chen ,  Tzyy-Jang Tseng ,  Ra-Min Tain

IPC: H01L23/16 ,  H01L23/66 ,  H01L23/00 ,  H01L23/31

Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.

公开(公告)号：US20190306987A1

公开(公告)日：2019-10-03

申请号：US16361180

申请日：2019-03-21

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Kai-Ming Yang ,  Chih-Lun Wang

IPC: H05K1/18 ,  H05K1/09 ,  H05K1/11 ,  H05K3/46 ,  H05K3/42 ,  H05K3/00 ,  H05K1/02

Abstract: A circuit board including an interconnect substrate and a multilayer structure is provided. The interconnect substrate includes a core layer and a conductive structure disposed on the core layer. The multilayer structure is disposed on the conductive structure. The multilayer structure includes a plurality of dielectric layers and a plurality of circuit structures. The circuit structures are disposed in the dielectric layers. A topmost layer in the circuit structures is exposed to the dielectric layers to be in contact with the conductive structure. A pattern of the topmost layer in the circuit structures and a pattern of a top surface of the conductive structure are engaged with each other.

公开(公告)号：US09484223B2

公开(公告)日：2016-11-01

申请号：US14985448

申请日：2015-12-31

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Chung-W. Ho

IPC: H01L21/00 ,  H01L21/48 ,  H01L21/683 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L21/4857 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2221/6835 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A coreless packaging substrate includes: a circuit buildup structure having at least a dielectric layer, a wiring layer and a plurality of conductive elements, a plurality of electrical pads embedded in the dielectric layer of the circuit buildup structure, a plurality of metal bumps formed on the wiring layer of the circuit buildup structure, and a dielectric passivation layer formed on the surface of the circuit buildup structure and the metal bumps with the metal bumps exposed from the dielectric passivation layer. The metal bumps each have a metal column portion and a wing portion integrally connected to the metal column portion, such that the bonding force between the metal bumps and a semiconductor chip can be enhanced by the entire top surface of the wing portions of the metal bumps being completely exposed.

Abstract translation: 无芯封装基板包括：具有至少介电层，布线层和多​​个导电元件的电路积层结构，嵌入电路堆积结构的电介质层中的多个电焊盘，形成在 电路积层结构的布线层，以及形成在电路堆积结构的表面上的电介质钝化层和金属凸块，金属凸块从电介质钝化层露出。 金属凸块各自具有金属柱部分和与金属柱部分一体地连接的翼部，使得金属凸块和半导体芯片之间的结合力可以通过金属凸块的翼部的整个顶表面增强 被完全暴露。

公开(公告)号：US20140099432A1

公开(公告)日：2014-04-10

申请号：US13727600

申请日：2012-12-27

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

IPC: H05K3/00

CPC classification number: H05K3/007 ,  H05K3/0097 ,  H05K3/381 ,  H05K2201/0154

Abstract: A fabrication method for a flexible circuit board is provided. The fabrication method includes the following steps. Firstly, a release film having an upper surface and a lower surface opposite to each other is provided. Next, two flexible substrates are respectively disposed on the upper surface and the lower surface. Next, a plurality of nano-scale micro-pores are formed on each flexible substrate to form two non-smooth flexible substrates. The nano-scale micro-pores evenly distributed over an outer surface of each non-smooth flexible substrate. Each non-smooth flexible substrate being adapted to be performed a plating process directly on the outer surface thereof.

Abstract translation: 提供了一种柔性电路板的制造方法。 制造方法包括以下步骤。 首先，提供具有彼此相对的上表面和下表面的剥离膜。 接下来，在上表面和下表面上分别设置两个柔性基板。 接下来，在每个柔性基板上形成多个纳米级微孔，以形成两个非平滑柔性基板。 纳米级微孔均匀分布在每个非光滑柔性基底的外表面上。 每个非光滑柔性基底适于在其外表面上直接进行电镀工艺。

公开(公告)号：US11943877B2

公开(公告)日：2024-03-26

申请号：US17684421

申请日：2022-03-02

Applicant: Unimicron Technology Corp.

Inventor： Wen-Yu Lin ,  Kai-Ming Yang ,  Chen-Hao Lin ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  Chin-Sheng Wang ,  Guang-Hwa Ma ,  Tzyy-Jang Tseng

IPC: H05K3/24 ,  H01L21/56 ,  H01L23/15 ,  H01L23/31 ,  H01L23/488 ,  H01L23/544 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K3/467 ,  H05K1/112 ,  H05K2201/0191

Abstract: A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.

公开(公告)号：US11860428B1

公开(公告)日：2024-01-02

申请号：US17835990

申请日：2022-06-09

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Tzyy-Jang Tseng

IPC: G02B6/42 ,  H01S5/42

CPC classification number: G02B6/4274 ,  G02B6/4249 ,  G02B6/4271 ,  G02B6/4295 ,  H01S5/423

Abstract: A package structure includes a circuit board, a package substrate, a fine metal L/S RDL-substrate, an electronic assembly, a photonic assembly, a heat dissipation assembly, and an optical fiber assembly. The package substrate is disposed on and electrically connected to the circuit board. The fine metal L/S RDL-substrate is disposed on and electrically connected to the package substrate. The electronic assembly includes an application specific integrated circuit (ASIC) assembly, an electronic integrated circuit (EIC) assembly, and a photonic integrated circuit (PIC) assembly which are respectively disposed on the fine metal L/S RDL-substrate and electrically connected to the package substrate by the fine metal L/S RDL-substrate. The heat dissipation assembly is disposed on the electronic assembly. The optical fiber assembly is disposed on the package substrate and electrically connected to the package substrate and the PIC assembly. A packaging method of the VCSEL array chip is presented.

公开(公告)号：US20230137841A1

公开(公告)日：2023-05-04

申请号：US18089465

申请日：2022-12-27

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Ra-Min Tain ,  Cheng-Ta Ko ,  Tzyy-Jang Tseng ,  Chun-Hsien Chien

IPC: H05K3/46 ,  H05K1/11 ,  H05K3/40 ,  H05K3/00

Abstract: A circuit carrier includes a substrate, a first build-up circuit structure, a second build-up circuit structure, a fine redistribution structure and at least one conductive through hole. The substrate has a top surface and a bottom surface opposite to each other. The first build-up circuit structure is disposed on the top surface of the substrate and electrically connected to the substrate. The second build-up circuit structure is disposed on the bottom surface of the substrate and electrically connected to the substrate. The fine redistribution structure is directly attached on the first build-up circuit structure, wherein a line width and a line spacing of the fine redistribution structure are smaller than those of the first build-up circuit structure. The conductive through hole penetrates the fine redistribution structure and a portion of the first build-up circuit structure and is electrically connected to the fine redistribution structure and the first build-up circuit structure.

公开(公告)号：US20230116522A1

公开(公告)日：2023-04-13

申请号：US18079884

申请日：2022-12-13

Applicant: Unimicron Technology Corp.

Inventor： Ming-Ru Chen ,  Tzyy-Jang Tseng ,  Cheng-Chung Lo

IPC: H01L25/16 ,  H01L33/62

Abstract: A manufacturing method of a light emitting diode (LED) package structure includes the following steps. A carrier is provided. A redistribution layer is formed on the carrier. A plurality of active devices are formed on the carrier. A plurality of LEDs are transferred on the redistribution layer. The LEDs and the active devices are respectively electrically connected to the redistribution layer. The active devices are adapted to drive the LEDs, respectively. A molding compound is formed on the redistribution layer to encapsulate the LEDs. The carrier is removed to expose a bottom surface of the redistribution layer.

公开(公告)号：US20220336333A1

公开(公告)日：2022-10-20

申请号：US17233551

申请日：2021-04-19

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Kai-Ming Yang ,  Chia-Yu Peng ,  Chi-Hai Kuo ,  Tzyy-Jang Tseng

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A package structure includes at least one first redistribution layer, at least one second redistribution layer, a chip pad, a solder ball pad, a chip, a solder ball, and a molding compound. The first redistribution layer includes a first dielectric layer and a first redistribution circuit that fills a first opening and a second opening of the first dielectric layer. The first dielectric layer is aligned with the first redistribution circuit. The second redistribution layer includes a second and a third dielectric layers and a second redistribution circuit. The third dielectric layer is aligned with the second redistribution circuit. The chip pad and the solder ball pad are electrically connected to the first and the second redistribution circuits respectively. The chip and the solder ball are disposed on the chip pad and the solder ball pad respectively. The molding compound at least covers the chip and the chip pad.