公开(公告)号：US10886241B1

公开(公告)日：2021-01-05

申请号：US17023967

申请日：2020-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Chu-Fu Lin ,  Ming-Tse Lin

IPC: H01L23/64 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.

公开(公告)号：US10818616B2

公开(公告)日：2020-10-27

申请号：US16361880

申请日：2019-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Chu-Fu Lin ,  Ming-Tse Lin

IPC: H01L23/64 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.

公开(公告)号：US20200243386A1

公开(公告)日：2020-07-30

申请号：US16258389

申请日：2019-01-25

Applicant: United Microelectronics Corp.

Inventor： CHU-FU LIN ,  Ming-Tse Lin ,  Chun-Hung Chen

IPC: H01L21/768 ,  H01L23/48 ,  H01L21/311

Abstract: A method for fabricating semiconductor device includes providing a preliminary device layer, having a substrate on top and a through substrate via (TSV) structure in the substrate. A top portion of the TSV structure protrudes out from the substrate. A dielectric layer is disposed over the substrate to cover the substrate and the TSV structure. A coating layer is formed over the dielectric layer, wherein the coating layer fully covers over the dielectric layer with a flat surface. An anisotropic etching process is performed to the coating layer and the dielectric layer without etching selection until the TSV structure is exposed.

公开(公告)号：US20200235063A1

公开(公告)日：2020-07-23

申请号：US16280938

申请日：2019-02-20

Applicant: United Microelectronics Corp.

Inventor： Chun-Hung Chen ,  Ming-Tse Lin

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Provided are a three-dimensional integrated circuit (3DIC) and a method of manufacturing the same. The 3DIC includes a first wafer, a second wafer, and a hybrid bonding structure. The second wafer is bonded to the first wafer by the hybrid bonding structure. The hybrid bonding structure includes a blocking layer between a hybrid bonding dielectric layer and a hybrid bonding metal layer.

公开(公告)号：US10153252B2

公开(公告)日：2018-12-11

申请号：US15269994

申请日：2016-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Tse Lin

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/768 ,  H01L21/20 ,  H01L25/00 ,  H01L21/18 ,  H01L23/48

Abstract: A wafer to wafer structure includes a first wafer, a second wafer. A first bonding layer and a second bonding layer are disposed between the first wafer and the second wafer. A plurality of first interconnects are disposed within the he first bonding layer. A plurality of second interconnects are disposed within the second bonding layer. An interface is disposed between the first bonding layer and the second bonding layer. At least a through silicon via penetrates the first wafer, the first bonding layer and the interface to enter the second bonding layer. The through silicon via contacts one of the first interconnects and one of the second interconnects.

公开(公告)号：US09437491B2

公开(公告)日：2016-09-06

申请号：US14791265

申请日：2015-07-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Tse Lin ,  Chu-Fu Lin ,  Chien-Li Kuo ,  Yung-Chang Lin

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/522 ,  H01L21/283 ,  H01L21/302 ,  H01L49/02

CPC classification number: H01L21/76898 ,  H01L21/283 ,  H01L21/302 ,  H01L21/7685 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76883 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/16 ,  H01L28/60 ,  H01L2224/02317 ,  H01L2224/0401 ,  H01L2224/4824 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening.

Abstract translation: 本发明提供一种用TSV电极形成芯片的方法。 提供具有第一表面和第二表面的基底。 从第二表面的一侧进行变薄处理，使得第二表面变成第三表面。 接下来，在衬底中形成穿过第一表面和第三表面的穿透。 图案化材料层形成在衬底上，其中图案化材料层具有开口以暴露穿透通孔。 导电层形成在第三表面上，从而同时在穿透孔中形成TSV电极和开口中的表面导电层。

公开(公告)号：US20160155685A1

公开(公告)日：2016-06-02

申请号：US14556215

申请日：2014-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Chien-Li Kuo ,  Ming-Tse Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/3065 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating through-substrate structure is disclosed. The method includes the steps of: providing a substrate; forming a through-substrate hole and a through-substrate trench in the substrate; and forming a metal layer in the through-substrate hole and the through-substrate trench for forming a through-substrate via and a through-substrate conductor having a void therein.

Abstract translation: 公开了一种用于制造贯穿衬底结构的方法。 该方法包括以下步骤：提供衬底; 在基板中形成贯通基板孔和贯通基板沟槽; 以及在贯通基板孔中形成金属层，以及在其中形成贯通基板通孔的贯通基板沟槽和形成有空隙的贯通基板导体。

公开(公告)号：US20160064314A1

公开(公告)日：2016-03-03

申请号：US14468329

申请日：2014-08-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Tse Lin ,  Kuei-Sheng Wu ,  Chien-Li Kuo

IPC: H01L23/498 ,  H01L21/311 ,  H01L21/48

CPC classification number: H01L23/49811 ,  H01L21/31111 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to an interposer structure and a manufacturing method thereof. The interposer structure includes a first dielectric layer, a conductive pad, and a bump. The conductive pad is disposed in the first dielectric layer, wherein a top surface of the conductive pad is exposed from a first surface of the first dielectric layer, the conductive pad further includes a plurality of connection feet, and the connection feet protrude from a bottom surface of the conductive pad to a second surface of the first dielectric layer. The bump is disposed on the second surface of the first dielectric layer, and the bump directly contacts to the connection feet. Through the aforementioned interposer structure, it is sufficient to achieve the purpose of improving the electrical performance of the semiconductor device and avoiding the signal being loss through the TSV.

Abstract translation: 本发明涉及内插器结构及其制造方法。 插入器结构包括第一电介质层，导电焊盘和凸块。 所述导电焊盘设置在所述第一电介质层中，其中所述导电焊盘的顶表面从所述第一介电层的第一表面露出，所述导电焊盘还包括多个连接脚，并且所述连接脚从底部突出 导电焊盘的表面到第一介电层的第二表面。 凸块设置在第一电介质层的第二表面上，凸块直接接触连接脚。 通过上述插入器结构，达到提高半导体器件的电气性能并避免信号通过TSV损耗的目的就足够了。

公开(公告)号：US09123789B2

公开(公告)日：2015-09-01

申请号：US13747492

申请日：2013-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Tse Lin ,  Chu-Fu Lin ,  Chien-Li Kuo ,  Yung-Chang Lin

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L21/76898 ,  H01L21/283 ,  H01L21/302 ,  H01L21/7685 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76883 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/16 ,  H01L28/60 ,  H01L2224/02317 ,  H01L2224/0401 ,  H01L2224/4824 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening.

Abstract translation: 本发明提供一种用TSV电极形成芯片的方法。 提供具有第一表面和第二表面的基底。 从第二表面的一侧进行变薄处理，使得第二表面变成第三表面。 接下来，在衬底中形成穿过第一表面和第三表面的穿透。 图案化材料层形成在衬底上，其中图案化材料层具有开口以暴露穿透通孔。 导电层形成在第三表面上，从而同时在穿透孔中形成TSV电极和开口中的表面导电层。

公开(公告)号：US09123730B2

公开(公告)日：2015-09-01

申请号：US13939184

申请日：2013-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo ,  Yung-Chang Lin ,  Ming-Tse Lin ,  Kuei-Sheng Wu ,  Chia-Fang Lin

IPC: H01L23/552 ,  H01L23/58 ,  H01L23/00 ,  H01L23/48 ,  H01L23/66

CPC classification number: H01L23/552 ,  H01L23/481 ,  H01L23/535 ,  H01L23/585 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention provides a semiconductor device with a shielding structure. The semiconductor device includes a substrate, an RF circuit, a shielding structure and an interconnection system. The substrate includes an active side and a back side. The RF circuit is disposed on the active side of the substrate. The shielding structure is disposed on the active side and encompasses the RF circuit. The shielding structure is grounded. The shielding structure includes a shielding TST which does not penetrate through the substrate. The interconnection system is disposed on the active side of the substrate. The interconnection system includes a connection unit providing a signal to the RF circuit.

Abstract translation: 本发明提供一种具有屏蔽结构的半导体器件。 半导体器件包括衬底，RF电路，屏蔽结构和互连系统。 基板包括有源侧和背面。 RF电路设置在基板的有源侧。 屏蔽结构设置在有源侧并且包围RF电路。 屏蔽结构接地。 屏蔽结构包括不穿透基板的屏蔽TST。 互连系统设置在基板的有源侧。 互连系统包括向RF电路提供信号的连接单元。