公开(公告)号：US09461818B2

公开(公告)日：2016-10-04

申请号：US14066350

申请日：2013-10-29

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

IPC: G06F11/30 ,  H04L9/08 ,  G06F12/08 ,  G06F21/52 ,  G06F21/71 ,  G06F21/72 ,  G06F9/30 ,  G06F21/60 ,  H04L9/06 ,  G06F21/54

CPC classification number: H04L9/0827 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/602 ,  G06F21/71 ,  G06F21/72 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

Abstract: A method for encrypting a program for subsequent execution by a microprocessor configured to decrypt and execute the encrypted program includes receiving an object file specifying an unencrypted program that includes conventional branch instructions whose target address may be determined pre-run time. The method also includes analyzing the program to obtain chunk information that divides the program into a sequence of chunks each comprising a sequence of instructions and that includes encryption key data associated with each of the chunks. The encryption key data associated with each of the chunks is distinct. The method also includes replacing each of the conventional branch instructions that specifies a target address that is within a different chunk than the chunk in which the conventional branch instruction resides with a branch and switch key instruction. The method also includes encrypting the program based on the chunk information.

Abstract translation: 用于加密被配置为解密和执行加密程序的微处理器后续执行的程序的方法包括接收指定未加密程序的目标文件，其包括其目标地址可以被确定为预先运行时间的常规分支指令。 该方法还包括分析程序以获得将程序划分成每个包括指令序列并且包括与每个块相关联的加密密钥数据的块的序列的块信息。 与每个块相关联的加密密钥数据是不同的。 该方法还包括用分支和切换键指令代替指定与常规分支指令所在的块不同的块内的目标地址的每个常规分支指令。 该方法还包括基于块信息来加密程序。

公开(公告)号：US09317301B2

公开(公告)日：2016-04-19

申请号：US14526029

申请日：2014-10-28

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

IPC: G06F9/445 ,  G06F9/28 ,  G06F9/44 ,  G06F9/30 ,  G06F9/26 ,  G06F9/38 ,  G06F15/82

CPC classification number: G06F9/441 ,  G06F9/265 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/4401 ,  G06F9/4403 ,  G06F15/82

Abstract: A microprocessor includes a plurality of registers that holds an architectural state of the microprocessor and an indicator that indicates a boot instruction set architecture (ISA) of the microprocessor as either the x86 ISA or the Advanced RISC Machines (ARM) ISA. The microprocessor also includes a hardware instruction translator that translates x86 ISA instructions and ARM ISA instructions into microinstructions. The hardware instruction translator translates, as instructions of the boot ISA, the initial ISA instructions that the microprocessor fetches from architectural memory space after receiving a reset signal. The microprocessor also includes an execution pipeline, coupled to the hardware instruction translator. The execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions. In response to the reset signal, the microprocessor initializes its architectural state in the plurality of registers as defined by the boot ISA prior to fetching the initial ISA instructions.

Abstract translation: 微处理器包括保持微处理器架构状态的多个寄存器和指示微处理器的引导指令集体系结构（ISA）作为x86 ISA或高级RISC机器（ARM）ISA的指示符。 微处理器还包括硬件指令转换器，将x86 ISA指令和ARM ISA指令转换为微指令。 作为引导ISA的指令，硬件指令转换器将转换为接收复位信号后微处理器从架构存储器空间中提取的初始ISA指令。 微处理器还包括耦合到硬件指令转换器的执行流水线。 执行流水线执行微指令以生成由x86 ISA和ARM ISA指令定义的结果。 响应于复位信号，微处理器在获取初始ISA指令之前初始化由引导ISA定义的多个寄存器中的架构状态。

公开(公告)号：US20150113250A1

公开(公告)日：2015-04-23

申请号：US14088620

申请日：2013-11-25

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30178 ,  G06F9/328 ,  G06F9/3891

Abstract: A microprocessor includes a plurality of memories each configured to hold microcode instructions. At least a first of the plurality of memories is configured to provide M-bit wide words of compressed microcode instructions, and at least a second of the plurality of memories is configured to provide N-bit wide words of uncompressed microcode instructions. M and N are integers greater than zero and N is greater than M. The microprocessor also includes a decompression unit configured to decompress the compressed microcode instructions after being fetched from the at least a first of the plurality of memories and before being executed.

Abstract translation: 微处理器包括多个存储器，每个存储器被配置为保持微码指令。 所述多个存储器中的至少第一个被配置为提供压缩微码指令的M位宽的字，并且所述多个存储器中的至少一个存储器被配置为提供未压缩的微代码指令的N位宽字。 M和N是大于零并且N大于M的整数。微处理器还包括解压缩单元，其被配置为在从多个存储器中的至少第一个存储器中取出并在执行之前解压缩压缩的微代码指令。

公开(公告)号：US20150067310A1

公开(公告)日：2015-03-05

申请号：US14281657

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Darius D. Gaskins

IPC: G06F9/44

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.

Abstract translation: 微处理器包括多个处理核心和配置寄存器，配置寄存器被配置为指示多个处理核心中的每一个是启用还是禁用。 所述多个处理核心中的每一个启用的一个处理核心被配置为在第一情况下读取配置寄存器，以确定多个处理核心中的哪一个被启用或禁用，并且基于配置寄存器的读取生成相应的配置相关值 一审。 配置寄存器被更新以指示多个处理核心中先前启用的一个处理核心被禁用。 所述多个处理核心中的每一个被配置为在第二实例中读取配置寄存器，以确定多个处理核心中的哪一个被启用或禁用，并且基于对配置寄存器的读取生成相应的配置相关值 第二例。

公开(公告)号：US20150067250A1

公开(公告)日：2015-03-05

申请号：US14281585

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks

IPC: G06F12/08

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of processing cores, a resource shared by the plurality of processing cores, and a hardware semaphore readable and writeable by each of the plurality of processing cores within a non-architectural address space. Each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained. Each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource.

Abstract translation: 微处理器包括多个处理核心，由多个处理核心共享的资源以及由非结构化地址空间内的多个处理核心中的每一个可读和写的硬件信号量。 多个处理核心中的每一个被配置为写入硬件信号量以请求所有权共享资源并从硬件信号量读取以确定是否获得所有权。 多个处理核心中的每一个被配置为写入硬件信号量以放弃共享资源的所有权。