公开(公告)号：US20050079675A1

公开(公告)日：2005-04-14

申请号：US10965763

申请日：2004-10-18

Applicant: Alper Ilkbahar ,  Roy Scheuerlein ,  Andrew Walker ,  Luca Fasoli

Inventor： Alper Ilkbahar ,  Roy Scheuerlein ,  Andrew Walker ,  Luca Fasoli

IPC: G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L29/792 ,  H01L21/00 ,  H01L21/31 ,  H01L21/469 ,  H01L21/84

CPC classification number: H01L29/66833 ,  G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L29/792

Abstract: An array of transistors includes a plurality of transistors, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction. Each transistor includes a source, a drain, a channel and a localized charge storage dielectric. A first transistor of the plurality of transistors and a second transistor of the plurality of transistors share a common source/drain. A first localized charge storage dielectric of the first transistor does not overlap the common source/drain and a second localized charge storage dielectric of the second transistor overlaps the common source/drain.

公开(公告)号：US20050078514A1

公开(公告)日：2005-04-14

申请号：US10675212

申请日：2003-09-30

Applicant: Roy Scheuerlein ,  Luca Fasoli ,  Mark Johnson

Inventor： Roy Scheuerlein ,  Luca Fasoli ,  Mark Johnson

IPC: G11C8/10 ,  G11C8/14 ,  G11C11/34 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C15/046 ,  G11C8/10 ,  G11C8/14 ,  G11C16/10 ,  G11C16/16

Abstract: Extremely dense memory cell structures provide for new array structures useful for implementing memory and logic functions. An exemplary non-volatile memory array includes a first plurality of X-lines configured to be logically identical in a read mode of operation, and each associated with a first Y-line group numbering at least one Y-line. Each of the first plurality of X-lines may also be associated with a second Y-line group numbering at least one Y-line. In some embodiments, the first and second Y-Line groups are simultaneously selectable in a read mode and, when so selected, are respectively coupled to true and complement inputs of a sense amplifier circuit. Such Y-line groups may number only one Y-line, or may number more than one Y-line. Many types of memory cells may be used, such as various passive element cells and EEPROM cells, in both 2D or 3D memory arrays. Such arrays may be configured as a memory to store data, or configured to perform threshold logic, or configured as a content addressable memory array.

Abstract translation: 非常密集的存储单元结构提供了用于实现内存和逻辑功能的新数组结构。 示例性非易失性存储器阵列包括被配置为在读取操作模式下在逻辑上相同的第一多个X线，并且每个X线与与至少一个Y线编号的第一Y线组相关联。 第一多个X线中的每一个也可以与编号至少一个Y线的第二Y线组相关联。 在一些实施例中，第一和第二Y线组可以以读取模式同时选择，并且当这样选择时，它们分别耦合到读出放大器电路的真实和补码输入。 这样的Y线组可以仅编号一条Y线，或者可以编号多于一条Y线。 可以在2D或3D存储器阵列中使用许多类型的存储单元，例如各种无源元件单元和EEPROM单元。 这样的阵列可以被配置为存储数据，或被配置为执行阈值逻辑或被配置为内容可寻址存储器阵列的存储器。

公开(公告)号：US20050073898A1

公开(公告)日：2005-04-07

申请号：US10994016

申请日：2004-11-19

Applicant: Roy Scheuerlein ,  N. Knall

Inventor： Roy Scheuerlein ,  N. Knall

IPC: G11C5/00 ,  G11C8/00 ,  G11C11/34 ,  G11C17/16 ,  H01L21/336

CPC classification number: G11C13/0014 ,  B82Y10/00 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/72

Abstract: In a passive element memory array, such as a rail stack array having a continuous semiconductor region along one or both of the array lines, programming a memory cell may disturb nearby memory cells as result of a leakage path along the array line from the selected cell to the adjacent cell. This effect may be reduced substantially by changing the relative timing of the programming pulses applied to the array lines for the selected memory cell, even if the voltages are unchanged. In an exemplary three-dimensional antifuse memory array, a positive-going programming pulse applied to the anode region of the memory cell preferably is timed to lie within the time that a more lightly-doped cathode region is pulsed low.

公开(公告)号：US20050044459A1

公开(公告)日：2005-02-24

申请号：US10961501

申请日：2004-10-08

Applicant: Roy Scheuerlein ,  Mark Johnson ,  Derek Bosch ,  Alper Ilkbahar ,  J. Tringali

Inventor： Roy Scheuerlein ,  Mark Johnson ,  Derek Bosch ,  Alper Ilkbahar ,  J. Tringali

IPC: G11C7/10 ,  G11C7/24 ,  G11C29/00 ,  G11C29/44

CPC classification number: G11C29/76 ,  G11C7/1006 ,  G11C7/24 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/78

Abstract: The preferred embodiments described herein relate to a redundant memory structure using bad bit pointers. In one preferred embodiment, data is written in a first plurality of memory cells, and an error is detected in writing data in one of the memory cells. In response to the detected error, a pointer is written in a second plurality of memory cells, the pointer identifying which memory cell in the first plurality of memory cells contains the error. During a read operation, the data is read from the first plurality of memory cells, and the pointer is read from the second plurality of memory cells. From the pointer, the memory cell containing the error is identified, and the error is corrected. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

公开(公告)号：US08575715B2

公开(公告)日：2013-11-05

申请号：US13571100

申请日：2012-08-09

Applicant: Andrei Mihnea ,  Deepak C. Sekar ,  George Samachisa ,  Roy Scheuerlein ,  Li Xiao

Inventor： Andrei Mihnea ,  Deepak C. Sekar ,  George Samachisa ,  Roy Scheuerlein ,  Li Xiao

IPC: H01L29/66

CPC classification number: G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/24

Abstract: A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P−/N+ device or a P+/N−/P+ device.

Abstract translation: 描述了一种用于形成使用穿通二极管作为与可逆电阻率切换元件串联的转向元件的存储系统的存储系统和方法。 穿通二极管允许交叉点存储器阵列的双极性操作。 穿通二极管可具有对称的非线性电流/电压关系。 穿通二极管在选择的电池的高偏压下具有高电流，对于未选择的电池，在低偏压下具有低泄漏电流。 因此，它与具有电阻式开关元件的交叉点存储器阵列中的双极开关兼容。 穿通二极管可以是N + / P- / N +器件或P + / N- / P +器件。

公开(公告)号：US08154904B2

公开(公告)日：2012-04-10

申请号：US12488159

申请日：2009-06-19

Applicant: Deepak C. Sekar ,  Klaus Schuegraf ,  Roy Scheuerlein

Inventor： Deepak C. Sekar ,  Klaus Schuegraf ,  Roy Scheuerlein

IPC: G11C11/00 ,  G11C8/00

CPC classification number: G11C13/0007 ,  G11C7/00 ,  G11C8/12 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0088 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72

Abstract: A storage system and method for operating the storage system that uses reversible resistance-switching elements is described. Techniques are disclosed herein for varying programming conditions to account for different resistances that memory cells have. These techniques can program memory cells in fewer attempts, which can save time and/or power. Techniques are disclosed herein for achieving a high programming bandwidth while reducing the worst case current and/or power consumption. In one embodiment, a page mapping scheme is provided that programs multiple memory cells in parallel in a way that reduces the worst case current and/or power consumption.

Abstract translation: 描述了一种用于操作使用可逆电阻切换元件的存储系统的存储系统和方法。 本文公开了用于改变编程条件以解决存储器单元具有的不同电阻的技术。 这些技术可以以较少的尝试编程存储器单元，这可以节省时间和/或功率。 本文公开了用于实现高编程带宽同时减少最坏情况下的电流和/或功率消耗的技术。 在一个实施例中，提供了以减少最坏情况下的电流和/或功率消耗的方式并行地编程多个存储器单元的页面映射方案。

公开(公告)号：US07851851B2

公开(公告)日：2010-12-14

申请号：US11691939

申请日：2007-03-27

Applicant: Nima Mokhlesi ,  Roy Scheuerlein

Inventor： Nima Mokhlesi ,  Roy Scheuerlein

IPC: H01L29/792

CPC classification number: H01L29/7881 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/7827 ,  H01L29/792 ,  H01L29/7926

Abstract: A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell, such that a defined boundary exists between the semiconductor active region of the first memory cell and the semiconductor active region of the second memory cell.

Abstract translation: 单片三维NAND串包括位于第二存储单元上的第一存储单元。 外部在第二存储单元的半导体有源区上形成第一存储单元的半导体有源区，使得在第一存储单元的半导体有源区和第二存储单元的半导体有源区之间存在限定的边界。

公开(公告)号：US07808038B2

公开(公告)日：2010-10-05

申请号：US11691858

申请日：2007-03-27

Applicant: Nima Mokhlesi ,  Roy Scheuerlein

Inventor： Nima Mokhlesi ,  Roy Scheuerlein

IPC: H01L29/792

CPC classification number: H01L27/115 ,  H01L27/11556 ,  H01L27/11568

Abstract: A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is a first pillar having a square or rectangular cross section when viewed from above, the first pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. A semiconductor active region of the second memory cell is a second pillar having a square or rectangular cross section when viewed from above, the second pillar located under the first pillar, the second pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. One second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar.

Abstract translation: 单片三维NAND串包括位于第二存储单元上的第一存储单元。 第一存储单元的半导体有源区是从上方观察时具有正方形或矩形截面的第一柱，第一柱是位于第二导电型半导体区之间的第一导电型半导体区。 第二存储单元的半导体有源区是当从上方观察时具有正方形或矩形横截面的第二柱，位于第一柱下方的第二柱，第二柱是位于第二导电型半导体 地区。 第一柱中的一个第二导电类型半导体区域接触第二柱中的一个第二导电类型半导体区域。

公开(公告)号：US20080237698A1

公开(公告)日：2008-10-02

申请号：US11691858

申请日：2007-03-27

Applicant: Nima Mokhlesi ,  Roy Scheuerlein

Inventor： Nima Mokhlesi ,  Roy Scheuerlein

IPC: H01L29/792

CPC classification number: H01L27/115 ,  H01L27/11556 ,  H01L27/11568

Abstract: A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is a first pillar having a square or rectangular cross section when viewed from above, the first pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. A semiconductor active region of the second memory cell is a second pillar having a square or rectangular cross section when viewed from above, the second pillar located under the first pillar, the second pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. One second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar.

Abstract translation: 单片三维NAND串包括位于第二存储单元上的第一存储单元。 第一存储单元的半导体有源区是从上方观察时具有正方形或矩形截面的第一柱，第一柱是位于第二导电型半导体区之间的第一导电型半导体区。 第二存储单元的半导体有源区是当从上方观察时具有正方形或矩形横截面的第二柱，位于第一柱下方的第二柱，第二柱是位于第二导电型半导体 地区。 第一柱中的一个第二导电类型半导体区域接触第二柱中的一个第二导电类型半导体区域。

公开(公告)号：US20070272913A1

公开(公告)日：2007-11-29

申请号：US11839490

申请日：2007-08-15

Applicant: Roy Scheuerlein

Inventor： Roy Scheuerlein

IPC: H01L47/00

CPC classification number: H01L27/2481 ,  G11C13/0004 ,  G11C2213/71 ,  H01L27/2409 ,  H01L27/2418 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: The invention provides for a nonvolatile memory cell comprising a heater layer in series with a phase change material, such as a chalcogenide. Phase change is achieved in chalcogenide memories by thermal means. Concentrating thermal energy in a relatively small volume assists this phase change. In the present invention, a layer in a pillar-shaped section of a memory cell is etched laterally, decreasing its cross-section. In this way the cross section of the contact area between the heater layer and the phase change material is reduced. In preferred embodiments, the laterally etched layer is the heater layer or a sacrificial layer. In a preferred embodiment, such a cell can be used in a monolithic three dimensional memory array.

Abstract translation: 本发明提供了一种非易失性存储单元，其包括与诸如硫族化物之类的相变材料串联的加热器层。 通过热法在硫族化物记忆中实现相变。 将热能集中在相对较小的体积中有助于此相变。 在本发明中，存储单元的柱状部分的层被横向蚀刻，从而减小其横截面。 以这种方式，加热器层和相变材料之间的接触区域的横截面减小。 在优选实施例中，横向蚀刻层是加热器层或牺牲层。 在优选实施例中，这样的单元可以用在单片三维存储器阵列中。