公开(公告)号：US20070048967A1

公开(公告)日：2007-03-01

申请号：US11212599

申请日：2005-08-29

申请人： Yusuke Kohyama

发明人： Yusuke Kohyama

IPC分类号： H01L21/76 ,  H01L21/425 ,  H01L21/8238

CPC分类号： H01L21/823878 ,  H01L21/26586 ,  H01L21/76237

摘要： A boron ion stream may be used to implant ions, such as boron ions, into the sidewalls of an active area, such as an NFET active area. The boron ion stream has both vertical tilt and horizontal rotation components relative to the sidewalls and/or the silicon device, to provide a better line of sight onto the sidewalls. This may allow components of the silicon device to be moved closer together without unduly reducing the effectiveness of boron doping of NFET active area sidewalls, and provides an improved line of sight of a boron ion stream onto the sidewalls of an NFET active area prior to filling the surrounding trench with STI material.

摘要翻译： 硼离子流可用于将诸如硼离子的离子注入到有源区域（例如NFET有源区）的侧壁中。 硼离子流相对于侧壁和/或硅器件具有垂直倾斜和水平旋转分量，以在侧壁上提供更好的视线。 这可以允许硅器件的组件移动得更近，而不会不适当地降低NFET有源区侧壁的硼掺杂的有效性，并且在填充之前提供硼离子流到NFET有源区的侧壁上的改善的视线 周边沟槽采用STI材质。

公开(公告)号：US06977228B2

公开(公告)日：2005-12-20

申请号：US10388495

申请日：2003-03-17

申请人： Yusuke Kohyama ,  Nobuo Hayasaka ,  Katsuya Okumura

发明人： Yusuke Kohyama ,  Nobuo Hayasaka ,  Katsuya Okumura

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8242 ,  H01L29/49 ,  H01L21/302

CPC分类号： H01L27/10873 ,  H01L21/28061 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823437 ,  H01L27/10861 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/4941 ,  H01L29/66545 ,  H01L29/6656

摘要： A gate insulation film is formed on a semiconductor substrate, gate electrodes are formed on the gate insulation film, and source/drain diffusion layers are formed. A silicon nitride films is formed on a side wall of the gate electrodes, a silicon oxide film is formed on the overall surface, and the silicon oxide film is etched back to have the same height as that of the gate electrodes so that the surface is flattened, and then the surface of the gate electrodes are etched by a predetermined thickness to form a first stepped portion from the silicon oxide film, the first stepped portion is filled up by a tungsten film, the surface of the tungsten film is etched by a predetermined thickness so that a second stepped portion is formed, and then the second stepped portion is filled by a silicon nitride films.

摘要翻译： 在半导体基板上形成栅极绝缘膜，在栅极绝缘膜上形成栅电极，形成源极/漏极扩散层。 在栅电极的侧壁上形成氮化硅膜，在整个表面上形成氧化硅膜，并将氧化硅膜回蚀刻成具有与栅电极相同的高度，使得表面为 然后将栅电极的表面蚀刻预定厚度，从氧化硅膜形成第一台阶部分，第一台阶部分被钨膜填充，钨膜的表面被 预定厚度，从而形成第二台阶部分，然后用氮化硅膜填充第二台阶部分。

公开(公告)号：US20050258485A1

公开(公告)日：2005-11-24

申请号：US10850106

申请日：2004-05-21

申请人： Yusuke Kohyama

发明人： Yusuke Kohyama

IPC分类号： H01L21/762 ,  H01L21/336 ,  H01L21/76 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/66628 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/78654

摘要： An isolated semiconductor device and method for producing the isolated semiconductor device in which the device includes a silicon-on-insulator (SOI) device formed on a substrate. A dielectric film is formed on the insulator and covers the SOI device. The dielectric film may be a single film or a multilayer film. The silicon layer of the SOI device may include a channel region and source/drain regions. The SOI device may further include a gate insulator disposed on the channel region of the silicon layer, a gate disposed on the gate insulator and sidewall spacers formed a side surface of the gate. The dielectric film may also be disposed on an edge portion of the silicon layer. The device structure may further include metallization lines connecting through the isolation dielectric to the gate and to the source/drain regions. According, the method may include the steps of forming an SOI device on a substrate, and forming a device isolation dielectric film on said insulator after forming said silicon-on-insulator device. The method may also include the steps of forming a silicon-on-insulator device on a substrate, and forming a single dielectric film on said insulator and covering silicon-on-insulator device.

摘要翻译： 一种用于制造隔离半导体器件的隔离半导体器件和方法，其中器件包括形成在衬底上的绝缘体上硅（SOI）器件。 在绝缘体上形成绝缘膜并覆盖SOI器件。 电介质膜可以是单膜或多层膜。 SOI器件的硅层可以包括沟道区和源极/漏极区。 SOI器件还可以包括设置在硅层的沟道区上的栅极绝缘体，设置在栅极绝缘体上的栅极和形成栅极侧表面的侧壁间隔物。 电介质膜也可以设置在硅层的边缘部分上。 器件结构还可以包括通过隔离电介质连接到栅极和源极/漏极区域的金属化线。 该方法可以包括以下步骤：在衬底上形成SOI器件，以及在形成所述绝缘体上硅器件之后，在所述绝缘体上形成器件隔离电介质膜。 该方法还可以包括以下步骤：在衬底上形成绝缘体上硅器件，并在所述绝缘体上形成单个电介质膜并覆盖绝缘体上硅器件。

公开(公告)号：US20050206002A1

公开(公告)日：2005-09-22

申请号：US11121976

申请日：2005-05-05

申请人： Hiroyuki Nitta ,  Yoshiaki Fukuzumi ,  Yusuke Kohyama

发明人： Hiroyuki Nitta ,  Yoshiaki Fukuzumi ,  Yusuke Kohyama

IPC分类号： H01L21/3213 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L23/532 ,  H01L27/108 ,  H01L21/4763 ,  H01L23/48

CPC分类号： H01L21/76846 ,  H01L21/32134 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  Y10S438/927 ,  H01L2924/00

摘要： In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

摘要翻译： 在半导体器件中，在设置在半导体衬底上的氧化硅膜的表面部分中形成布线图案槽。 布线层被埋入布线图案槽中，其间插入阻挡金属膜。 从布线图形槽的各侧壁部选择性地去除阻挡金属膜。 换句话说，阻挡金属膜仅留在布线图案槽的底部。 因此，可以在半导体器件中形成具有在布线图案槽的每个侧壁和布线层的每一侧之间的介电常数低的中空部的镶嵌布线层。

公开(公告)号：US06906419B2

公开(公告)日：2005-06-14

申请号：US09883210

申请日：2001-06-19

申请人： Hiroyuki Nitta ,  Yoshiaki Fukuzumi ,  Yusuke Kohyama

发明人： Hiroyuki Nitta ,  Yoshiaki Fukuzumi ,  Yusuke Kohyama

IPC分类号： H01L21/3213 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L23/532 ,  H01L27/108 ,  H01L29/76 ,  H01L29/00

CPC分类号： H01L21/76846 ,  H01L21/32134 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  Y10S438/927 ,  H01L2924/00

摘要： In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

公开(公告)号：US06812542B2

公开(公告)日：2004-11-02

申请号：US09892713

申请日：2001-06-28

申请人： Yusuke Kohyama

发明人： Yusuke Kohyama

IPC分类号： H01L2900

CPC分类号： H01L27/10894 ,  H01L23/5252 ,  H01L27/10814 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises capacitor structures, each having a first lower electrode, a first insulating film formed on the first lower electrode and a first upper electrode formed on the first insulating film, and electric fuse elements, each having a second lower electrode, a second insulating film formed on the second lower electrode and having an impurity concentration higher than that of the first insulating film, and a second upper electrode formed on the second insulating film. The electric fuse elements have substantially the same structure as that of the capacitor structures, and they are formed on the same level as that of the capacitor structures. A writing voltage of the electric fuse element is determined by dielectric breakdown resistance of the second insulating film, which depends on the impurity concentration of the second insulating film.

摘要翻译： 半导体器件包括电容器结构，每个电容器结构具有第一下电极，形成在第一下电极上的第一绝缘膜和形成在第一绝缘膜上的第一上电极，电熔丝元件分别具有第二下电极，第二下电极 绝缘膜，形成在第二下电极上，其杂质浓度高于第一绝缘膜的杂质浓度;以及第二上电极，形成在第二绝缘膜上。 电熔丝元件具有与电容器结构基本相同的结构，并且它们形成在与电容器结构相同的水平上。 电熔丝元件的写入电压由第二绝缘膜的绝缘击穿电阻决定，其取决于第二绝缘膜的杂质浓度。

公开(公告)号：US06534814B2

公开(公告)日：2003-03-18

申请号：US09497690

申请日：2000-02-04

申请人： Junichiro Iba ,  Yusuke Kohyama

发明人： Junichiro Iba ,  Yusuke Kohyama

IPC分类号： H01L27108

CPC分类号： H01L27/10861

摘要： The invention provides a structure which enables a junction leak current to be reduced without reducing a capacitor area. A trench is formed in the surface of a substrate such that it is connected to a conductive region for a transistor. The structure is characterized by comprising a capacitor electrode formed on the inner peripheral surface of the trench and having its upper edge portion located below the conductive region, an insulating layer projecting inward of the trench at least from the upper edge portion of the capacitor electrode to the conductive region, thereby narrowing the diameter of the trench, a capacitor insulating film coated on the capacitor electrode, and a capacitor electrode filling the trench and contacting the capacitor insulating film.

摘要翻译： 本发明提供能够在不减小电容器面积的情况下降低结漏电流的结构。 在衬底的表面中形成沟槽，使得其连接到晶体管的导电区域。 该结构的特征在于，包括形成在沟槽的内周面上的电容电极，其上缘部位于导电区域的下方，绝缘层至少从电容电极的上缘部向内突出， 导电区域，从而使沟槽的直径变窄，涂覆在电容器电极上的电容器绝缘膜，以及填充沟槽并接触电容器绝缘膜的电容器电极。

公开(公告)号：US06329683B2

公开(公告)日：2001-12-11

申请号：US09748132

申请日：2000-12-27

申请人： Yusuke Kohyama

发明人： Yusuke Kohyama

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  G11C11/404 ,  H01L27/10852

摘要： In this DRAM, an SiO2 film for assuring the step coverage of cell-capacitor of cylinder type is left remained only in the peripheral circuit region. The capacitor upper electrode is formed extending from the memory cell array region to the peripheral circuit region. Since the capacitor upper electrode in the peripheral circuit region is disposed higher than the upper surface of the capacitor upper electrode which constitutes the cell-capacitor, this capacitor upper electrode in the peripheral circuit region is employed as a stopper for subsequently flattening the interlayer insulating film. Subsequently, the interlayer insulating film is employed as a mask for etching the capacitor upper electrode in the peripheral circuit region.

公开(公告)号：US06175130B1

公开(公告)日：2001-01-16

申请号：US09447813

申请日：1999-11-23

申请人： Keiji Hosotani ,  Yusuke Kohyama

发明人： Keiji Hosotani ,  Yusuke Kohyama

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L28/55 ,  H01L28/82 ,  H01L28/90

摘要： Provided is a semiconductor device and a method of manufacturing the semiconductor device having a stacked type capacitor excellent in storage capacity, breakdown voltage and reliability. A storage node electrode (Ru) of the stacked-type capacitor is formed on a contact hole of the underlying insulating film by the steps of forming the side wall of the contact hole diagonally at a taper angle within the range of 90 to 110°, forming a storage node electrode on the inner wall surface of the contact hole, filling SOG in the contact hole, etching off the Ru film on the insulating film using SOG as a mask, and etching off the Ru film formed on the upper peripheral region of the inner wall in the depth direction of the contact hole. Thereafter, the dielectric film of the stacked-type capacitor formed of a (Ba, Sr) TiO3 thin film is formed on the Ru storage node electrode. In this manner, it is possible to obtain a stack-type capacitor having a drastically-improved step coverage and a high breakdown voltage. In addition, it is easy to reduce the distance between adjacent Ru storage node electrodes within a resolution limit of lithography, compared to the conventional method.

摘要翻译： 提供一种半导体器件和制造具有存储容量，击穿电压和可靠性优异的堆叠型电容器的半导体器件的方法。 层叠型电容器的存储节点电极（Ru）通过以下步骤形成在下面的绝缘膜的接触孔上：将接触孔的侧壁对角地形成在90°至110°的范围内的锥角， 在接触孔的内壁表面上形成存储节点电极，在接触孔中填充SOG，使用SOG作为掩模蚀刻绝缘膜上的Ru膜，并且蚀刻形成在上部周边区域上的Ru膜 接触孔深度方向的内壁。 此后，在Ru储存节点电极上形成由（Ba，Sr）TiO 3薄膜形成的层叠型电容器的电介质膜。 以这种方式，可以获得具有急剧改善的台阶覆盖和高击穿电压的堆叠型电容器。 此外，与常规方法相比，在光刻的分辨率极限内容易地减小相邻Ru存储节点电极之间的距离。

公开(公告)号：US6153476A

公开(公告)日：2000-11-28

申请号：US30127

申请日：1998-02-25

申请人： Satoshi Inaba ,  Tohru Ozaki ,  Yusuke Kohyama ,  Kazumasa Sunouchi

发明人： Satoshi Inaba ,  Tohru Ozaki ,  Yusuke Kohyama ,  Kazumasa Sunouchi

IPC分类号： H01L21/8234 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/088 ,  H01L27/105 ,  H01L27/108 ,  H01L21/336

CPC分类号： H01L27/10844 ,  H01L27/105 ,  H01L27/108 ,  Y10S257/90

摘要： In a DRAM, a plurality of first MOSFETs are formed in a cell region on a semiconductor substrate based on the minimum design rule, and a first gate side-wall having a side-wall insulation film is formed on the side-wall portion of a first gate electrode of each of the first MOSFETs. At least one second MOSFET is formed in a peripheral circuit region on the semiconductor substrate, and a second gate side-wall having side-wall insulation films is formed on the side-wall portion of a second gate electrode of the second MOSFET. Both the first MOSFETs, which is capable of forming a fine contact hole self-aligned with the first gate electrode, and the second MOSFET, which is capable of sufficiently mitigating the parasitic resistance while suppressing the short channel effect, can be formed on the same substrate.