公开(公告)号：US6100130A

公开(公告)日：2000-08-08

申请号：US825993

申请日：1997-04-04

申请人： Junichiro Iba ,  Yusuke Kohyama

发明人： Junichiro Iba ,  Yusuke Kohyama

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10861

摘要： The invention provides a structure which enables a junction leak current to be reduced without reducing a capacitor area. A trench is formed in the surface of a substrate such that it is connected to a conductive region for a transistor. The structure is characterized by comprising a capacitor electrode formed on the inner peripheral surface of the trench and having its upper edge portion located below the conductive region, an insulating layer projecting inward of the trench at least from the upper edge portion of the capacitor electrode to the conductive region, thereby narrowing the diameter of the trench, a capacitor insulating film coated on the capacitor electrode, and a capacitor electrode filling the trench and contacting the capacitor insulating film.

摘要翻译： 本发明提供能够在不减小电容器面积的情况下降低结漏电流的结构。 在衬底的表面中形成沟槽，使得其连接到晶体管的导电区域。 该结构的特征在于，包括形成在沟槽的内周面上的电容电极，其上缘部位于导电区域的下方，绝缘层至少从电容电极的上缘部向内突出， 导电区域，从而使沟槽的直径变窄，涂覆在电容器电极上的电容器绝缘膜，以及填充沟槽并接触电容器绝缘膜的电容器电极。

公开(公告)号：US06534814B2

公开(公告)日：2003-03-18

申请号：US09497690

申请日：2000-02-04

申请人： Junichiro Iba ,  Yusuke Kohyama

发明人： Junichiro Iba ,  Yusuke Kohyama

IPC分类号： H01L27108

CPC分类号： H01L27/10861

摘要： The invention provides a structure which enables a junction leak current to be reduced without reducing a capacitor area. A trench is formed in the surface of a substrate such that it is connected to a conductive region for a transistor. The structure is characterized by comprising a capacitor electrode formed on the inner peripheral surface of the trench and having its upper edge portion located below the conductive region, an insulating layer projecting inward of the trench at least from the upper edge portion of the capacitor electrode to the conductive region, thereby narrowing the diameter of the trench, a capacitor insulating film coated on the capacitor electrode, and a capacitor electrode filling the trench and contacting the capacitor insulating film.

摘要翻译： 本发明提供能够在不减小电容器面积的情况下降低结漏电流的结构。 在衬底的表面中形成沟槽，使得其连接到晶体管的导电区域。 该结构的特征在于，包括形成在沟槽的内周面上的电容电极，其上缘部位于导电区域的下方，绝缘层至少从电容电极的上缘部向内突出， 导电区域，从而使沟槽的直径变窄，涂覆在电容器电极上的电容器绝缘膜，以及填充沟槽并接触电容器绝缘膜的电容器电极。

公开(公告)号：US06600189B1

公开(公告)日：2003-07-29

申请号：US09598379

申请日：2000-06-21

申请人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Junichiro Iba

发明人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Junichiro Iba

IPC分类号： H01L27108

CPC分类号： H01L27/1087 ,  H01L28/84 ,  Y10S438/909

摘要： A semiconductor device includes a semiconductor substrate having a trench on a surface thereof and an embedding member embedding the interior of the trench therewith. While the section of the trench when cut by a first plane perpendicular to the direction of the depth of the trench is defined as a first section and the section of the trench when cut by a second plane perpendicular to the direction of the depth of the trench and closer to the bottom of the trench than the first plane is defined as a second section, the area of the first section is smaller than that of the second section and a minimum radius of curvature of the first section is smaller than a minimum radius of curvature of the second section. As a result, it is possible to lessen the concentration of the electric field into the bottom of the trench.

摘要翻译： 半导体器件包括在其表面上具有沟槽的半导体衬底和嵌入沟槽内部的嵌入构件。 虽然当垂直于沟槽深度方向的第一平面切割沟槽的部分被定义为第一部分，并且当垂直于沟槽深度方向的第二平面切割沟槽的部分时 并且比所述第一平面更靠近所述沟槽的底部被限定为第二部分，所述第一部分的面积小于所述第二部分的面积，并且所述第一部分的最小曲率半径小于所述第一部分的最小半径 第二部分的曲率。 结果，可以减小进入沟槽底部的电场的浓度。

公开(公告)号：US06313535B1

公开(公告)日：2001-11-06

申请号：US09268678

申请日：1999-03-16

申请人： Junichiro Iba ,  Masaki Narita ,  Tomio Katata

发明人： Junichiro Iba ,  Masaki Narita ,  Tomio Katata

IPC分类号： H01L2348

CPC分类号： H01L21/7685 ,  H01L21/76805 ,  H01L21/76843 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wiring layer of a semiconductor integrated circuit comprises a first conductive film made of a material containing Al. A material, which reacts with Al at a rate lower than that at which Ti reacts with Al, is provided on the first conductive film. A first barrier metal film is formed, and an interlayer insulating film is formed thereon. An opening is formed in the interlayer insulating film so as to expose the first barrier metal film. The opening is buried to form a second conductive film electrically connected to the first conductive film.

摘要翻译： 半导体集成电路的布线层包括由含有Al的材料制成的第一导电膜。 与Al反应的速度低于Ti的材料与Al反应的材料设置在第一导电膜上。 形成第一阻挡金属膜，并在其上形成层间绝缘膜。 在层间绝缘膜中形成开口以露出第一阻挡金属膜。 掩模开口以形成与第一导电膜电连接的第二导电膜。

公开(公告)号：US06440644B1

公开(公告)日：2002-08-27

申请号：US09438061

申请日：1999-11-10

申请人： Takashi Sato ,  Katsuya Okumura ,  Junichiro Iba

发明人： Takashi Sato ,  Katsuya Okumura ,  Junichiro Iba

IPC分类号： G03C500

CPC分类号： G03F7/2026

摘要： A method and system for planarization is disclosed. The system includes a mask including a medium density, sub-resolution region which allows less than the full intensity of the exposing radiation through to a resist layer. By including multiple density regions, improved planarization can be achieved.

摘要翻译： 公开了一种用于平坦化的方法和系统。 该系统包括掩模，该掩模包括中等密度的亚分辨率区域，其允许小于通过抗蚀剂层的曝光辐射的全部强度。 通过包括多个密度区域，可以实现改进的平坦化。

公开(公告)号：US06288556B1

公开(公告)日：2001-09-11

申请号：US09204309

申请日：1998-12-03

申请人： Takashi Sato ,  Keita Asanuma ,  Junichiro Iba ,  Toru Ozaki ,  Hiroshi Nomura ,  Tatsuhiko Higashiki

发明人： Takashi Sato ,  Keita Asanuma ,  Junichiro Iba ,  Toru Ozaki ,  Hiroshi Nomura ,  Tatsuhiko Higashiki

IPC分类号： G01R2714

CPC分类号： G03F7/70633 ,  G03F7/70658 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention allows for measurement at the same density as an actual device pattern and measures the level of registration of actual patterns with precision. In the measurement of the invention, a first exposure process is performed on a first-level pattern and a second exposure process is then performed on a second-level pattern. After that, the patterns are developed and etched, thereby forming two patterns of different shapes. Next, the resistance between terminals of a pattern which are obtained by means of etching is measured through a four-point measurement. An amount of misregistration of the first-level pattern and the second-level pattern is calculated from the measured resistance.

摘要翻译： 本发明允许以与实际装置图案相同的密度进行测量，并且精确地测量实际图案的配准水平。 在本发明的测量中，对第一级图案执行第一曝光处理，然后对第二级图案执行第二曝光处理。 之后，显影和蚀刻图案，从而形成两种不同形状的图案。 接下来，通过四点测量来测量通过蚀刻获得的图案的端子之间的电阻。 从测量的电阻计算出第一电平图案和第二电平图案的重合不良。

公开(公告)号：US6107135A

公开(公告)日：2000-08-22

申请号：US21993

申请日：1998-02-11

申请人： Richard L. Kleinhenz ,  Gary B. Bronner ,  Junichiro Iba

发明人： Richard L. Kleinhenz ,  Gary B. Bronner ,  Junichiro Iba

IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/1087

摘要： A method of forming a buried plate electrode for a trench capacitor of a semiconductor memory device is provided. Trenches are formed in a semiconductor substrate and a dopant source film is formed on the sidewalls and bottom walls of the trenches. A resist is formed on the dopant source film which fills in the trenches. The resist is recessed to remain in the trenches at a level which is below the surface of the semiconductor substrate. Impurities are implanted into the semiconductor substrate using the recessed resist as a block mask. The dopant source film is etched using the recessed resist as an etching mask and the recessed resist is then removed. The implanted impurities and dopants from the dopant source film are diffused into the semiconductor substrate to form a buried plate electrode.

摘要翻译： 提供一种形成用于半导体存储器件的沟槽电容器的掩埋板电极的方法。 沟槽形成在半导体衬底中，并且掺杂剂源膜形成在沟槽的侧壁和底壁上。 在填充沟槽的掺杂剂源膜上形成抗蚀剂。 抗蚀剂凹陷以在半导体衬底的表面下方的水平保留在沟槽中。 使用凹陷的抗蚀剂作为阻挡掩模将杂质注入到半导体衬底中。 使用凹陷的抗蚀剂作为蚀刻掩模蚀刻掺杂剂源膜，然后除去凹陷的抗蚀剂。 来自掺杂剂源膜的注入杂质和掺杂剂扩散到半导体衬底中以形成掩埋板电极。

公开(公告)号：US6100132A

公开(公告)日：2000-08-08

申请号：US106082

申请日：1998-06-29

申请人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Junichiro Iba

发明人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Junichiro Iba

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/1087 ,  H01L28/84 ,  Y10S438/909

摘要： A semiconductor device includes a semiconductor substrate having a trench on a surface thereof and an embedding member embedding the interior of the trench therewith. While the section of the trench when cut by a first plane perpendicular to the direction of the depth of the trench is defined as a first section and the section of the trench when cut by a second plane perpendicular to the direction of the depth of the trench and closer to the bottom of the trench than the first plane is defined as a second section, the area of the first section is smaller than that of the second section and a minimum radius of curvature of the first section is smaller than a minimum radius of curvature of the second section. As a result, it is possible to lessen the concentration of the electric field into the bottom of the trench.

摘要翻译： 半导体器件包括在其表面上具有沟槽的半导体衬底和嵌入沟槽内部的嵌入构件。 虽然当垂直于沟槽深度方向的第一平面切割沟槽的部分被定义为第一部分，并且当垂直于沟槽深度方向的第二平面切割沟槽的部分时 并且比所述第一平面更靠近所述沟槽的底部被限定为第二部分，所述第一部分的面积小于所述第二部分的面积，并且所述第一部分的最小曲率半径小于所述第一部分的最小半径 第二部分的曲率。 结果，可以减小进入沟槽底部的电场的浓度。

公开(公告)号：US6064466A

公开(公告)日：2000-05-16

申请号：US950434

申请日：1997-10-15

申请人： Takashi Sato ,  Katsuya Okumura ,  Junichiro Iba

发明人： Takashi Sato ,  Katsuya Okumura ,  Junichiro Iba

IPC分类号： G03F7/11 ,  G03F1/00 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3105 ,  G03D27/42

CPC分类号： H01L21/31055 ,  G03F1/50 ,  H01L21/0273

摘要： A method and system for planarization of a semiconductor wafer is disclosed. The disclosed system includes a mask with at least a medium density pattern, where the pattern dimensions are below the resolving power of an exposure system. Less than full intensity of the exposing radiation passes through the medium density pattern of the mask to a resist layer and does not completely expose the underlying resist. Through adapting at least a portion of the mask to account for surface irregularities of a wafer's surface, improved planarization of the surface is achieved.

摘要翻译： 公开了一种用于半导体晶片平坦化的方法和系统。 所公开的系统包括具有至少中密度图案的掩模，其中图案尺寸低于曝光系统的分辨率。 曝光辐射的不足全部强度通过掩模的中等密度图案到抗蚀剂层，并且不完全暴露下面的抗蚀剂。 通过适应掩模的至少一部分以解决晶片表面的表面不规则性，实现了表面的改进的平坦化。

公开(公告)号：US6011611A

公开(公告)日：2000-01-04

申请号：US186368

申请日：1998-11-05

申请人： Hiroshi Nomura ,  Takashi Sato ,  Takuya Kono ,  Junichiro Iba

发明人： Hiroshi Nomura ,  Takashi Sato ,  Takuya Kono ,  Junichiro Iba

IPC分类号： G01B11/00 ,  G01M11/00 ,  G01M11/02 ,  G03F7/20 ,  G03F7/26 ,  H01L21/027 ,  G03B27/54 ,  G03B27/42 ,  G03C5/00

CPC分类号： G03F7/706 ,  G03F7/70633

摘要： The method of measuring the aberration of the projection optics, according to the present invention includes the following steps. In the first step, the first mask pattern including the first pattern in which a line and space pattern is arranged on a photomask to be linearly symmetrical, and the second pattern in which line patterns having a large line width are arranged on outer sides of the first pattern, to be linearly symmetrical, is transferred on a substrate. In the second step, the second mask pattern in which a patter designed to leave a part of the first pattern and a pattern designed to leave the entire second pattern are arranged to be linearly symmetrical, is transferred on the same substrate, so as to superimpose it on the transferred first pattern. In the third step, the position of the transferred pattern of the second pattern, and the predetermined position of the pattern section of the transferred pattern of the first pattern, which is left in the second step are detected. Thus, from the difference between these positions detected in the third step, the aberration of the projecting optics which is situated between the mask pattern of the photomask and the substrate is measured.

摘要翻译： 根据本发明的测量投影光学器件的像差的方法包括以下步骤。 在第一步骤中，包括在光掩模上布置线状和空间图案为线性对称的第一图案的第一掩模图案和其中具有大线宽的线图案布置在第二图案的第二图案上 线性对称的第一图案被转印到基板上。 在第二步骤中，其中设计成留下第一图案的一部分的图案和设计成保留整个第二图案的图案被布置为线性对称的第二掩模图案被转印在同一基板上，以便叠加 它在转移的第一种模式。 在第三步骤中，检测第二图案的转印图案的位置以及在第二步骤中留下的第一图案的转印图案的图案部分的预定位置。 因此，从第三步骤中检测到的这些位置之间的差异，测量位于光掩模的掩模图案和基板之间的投影光学器件的像差。