公开(公告)号：US6100130A

公开(公告)日：2000-08-08

申请号：US825993

申请日：1997-04-04

申请人： Junichiro Iba ,  Yusuke Kohyama

发明人： Junichiro Iba ,  Yusuke Kohyama

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10861

摘要： The invention provides a structure which enables a junction leak current to be reduced without reducing a capacitor area. A trench is formed in the surface of a substrate such that it is connected to a conductive region for a transistor. The structure is characterized by comprising a capacitor electrode formed on the inner peripheral surface of the trench and having its upper edge portion located below the conductive region, an insulating layer projecting inward of the trench at least from the upper edge portion of the capacitor electrode to the conductive region, thereby narrowing the diameter of the trench, a capacitor insulating film coated on the capacitor electrode, and a capacitor electrode filling the trench and contacting the capacitor insulating film.

摘要翻译： 本发明提供能够在不减小电容器面积的情况下降低结漏电流的结构。 在衬底的表面中形成沟槽，使得其连接到晶体管的导电区域。 该结构的特征在于，包括形成在沟槽的内周面上的电容电极，其上缘部位于导电区域的下方，绝缘层至少从电容电极的上缘部向内突出， 导电区域，从而使沟槽的直径变窄，涂覆在电容器电极上的电容器绝缘膜，以及填充沟槽并接触电容器绝缘膜的电容器电极。

公开(公告)号：US06534814B2

公开(公告)日：2003-03-18

申请号：US09497690

申请日：2000-02-04

申请人： Junichiro Iba ,  Yusuke Kohyama

发明人： Junichiro Iba ,  Yusuke Kohyama

IPC分类号： H01L27108

CPC分类号： H01L27/10861

摘要： The invention provides a structure which enables a junction leak current to be reduced without reducing a capacitor area. A trench is formed in the surface of a substrate such that it is connected to a conductive region for a transistor. The structure is characterized by comprising a capacitor electrode formed on the inner peripheral surface of the trench and having its upper edge portion located below the conductive region, an insulating layer projecting inward of the trench at least from the upper edge portion of the capacitor electrode to the conductive region, thereby narrowing the diameter of the trench, a capacitor insulating film coated on the capacitor electrode, and a capacitor electrode filling the trench and contacting the capacitor insulating film.

摘要翻译： 本发明提供能够在不减小电容器面积的情况下降低结漏电流的结构。 在衬底的表面中形成沟槽，使得其连接到晶体管的导电区域。 该结构的特征在于，包括形成在沟槽的内周面上的电容电极，其上缘部位于导电区域的下方，绝缘层至少从电容电极的上缘部向内突出， 导电区域，从而使沟槽的直径变窄，涂覆在电容器电极上的电容器绝缘膜，以及填充沟槽并接触电容器绝缘膜的电容器电极。

公开(公告)号：US07514752B2

公开(公告)日：2009-04-07

申请号：US11211604

申请日：2005-08-26

申请人： Yusuke Kohyama

发明人： Yusuke Kohyama

IPC分类号： H01L29/76

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823871

摘要： Methods and apparatus are described that reduce the possibility that unintended subway short-circuits will occur between contacts of different potentials along the boundary between tensile and compressive liners (the T-C boundary). This may be done without unduly increasing the size of the semiconductor device, or even increasing the size at all over previous designs. For example, simply by adjusting the layout of the device, the contacts of two different common gates may be offset in opposing directions relative to the T-C boundary. Or, by forming a T-C boundary having a zigzag or other similar pattern, the contacts may be arranged even closer together while still reducing the likelihood of short-circuiting subways forming. Such layout adjustments do not otherwise require any additional steps or cost.

摘要翻译： 描述了减少在拉伸和压缩衬里（T-C边界）之间的边界处的不同电位的触点之间发生意外的地铁短路的可能性。 这可以在不过度增加半导体器件的尺寸的情况下进行，或者甚至在以前的设计中增加尺寸。 例如，简单地通过调整装置的布局，两个不同公共栅极的触点可以相对于T-C边界相反的方向偏移。 或者，通过形成具有锯齿形或其他类似图案的T-C边界，可以将触点设置得更靠近在一起，同时仍然减少了地铁短路形成的可能性。 这样的布局调整不需要额外的步骤或成本。

公开(公告)号：US07163894B2

公开(公告)日：2007-01-16

申请号：US10927079

申请日：2004-08-27

申请人： Hiroyuki Nitta ,  Yoshiaki Fukuzumi ,  Yusuke Kohyama

发明人： Hiroyuki Nitta ,  Yoshiaki Fukuzumi ,  Yusuke Kohyama

IPC分类号： H01L21/4763

CPC分类号： H01L21/76846 ,  H01L21/32134 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  Y10S438/927 ,  H01L2924/00

摘要： In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

公开(公告)号：US20060124980A1

公开(公告)日：2006-06-15

申请号：US11333412

申请日：2006-01-18

申请人： Yusuke Kohyama ,  Takashi Ohsawa ,  Shizuo Sawada

发明人： Yusuke Kohyama ,  Takashi Ohsawa ,  Shizuo Sawada

IPC分类号： H01L29/94

CPC分类号： H01L27/10888 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

摘要： First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.

公开(公告)号：US06303429B1

公开(公告)日：2001-10-16

申请号：US09676084

申请日：2000-10-02

申请人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

发明人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

IPC分类号： H01L218242

CPC分类号： H01L27/10885 ,  H01L27/10852 ,  H01L27/10873 ,  H01L28/91

摘要： Capacitors are formed in the trenches made in an interlayer insulator made of silicon oxide. An insulating film (e.g., a silicon nitride film) is provided on the sides of each trench of the interlayer insulator. A storage electrode made of ruthenium or the like is provided in each trench of the interlayer insulator. A capacitor insulating film made of BSTO or the like is formed on the storage electrode. A plate electrode made of ruthenium or the like is formed on the capacitor insulating film. The plate electrode is common to all capacitors provided. Any two adjacent capacitors are electrically isolated by the interlayer insulator and the insulating film provided on the sides of the trenches of the interlayer insulator.

摘要翻译： 电容器形成在由氧化硅制成的层间绝缘体中制成的沟槽中。 绝缘膜（例如，氮化硅膜）设置在层间绝缘体的每个沟槽的侧面上。 在层间绝缘体的每个沟槽中设置由钌等制成的存储电极。 在存储电极上形成由BSTO等构成的电容绝缘膜。 在电容器绝缘膜上形成由钌等制成的平板电极。 平板电极对所有提供的电容器是共同的。 任何两个相邻的电容器通过层间绝缘体和设置在层间绝缘体的沟槽的侧面上的绝缘膜电隔离。

公开(公告)号：US06225230B1

公开(公告)日：2001-05-01

申请号：US08861736

申请日：1997-05-22

申请人： Hiroyuki Nitta ,  Yusuke Kohyama

发明人： Hiroyuki Nitta ,  Yusuke Kohyama

IPC分类号： H01L2100

CPC分类号： H01L21/76229

摘要： Disclosed is a method of forming an element isolation insulating film by STI (shallow trench isolation) method, which permits effectively preventing a concave portion from being formed in an edge of the element isolation insulating film, permits decreasing the number of treating steps, and also permits facilitating the formation of the element isolation insulating film with a high yield. In forming the element isolation insulating film, a groove is formed in a surface region of a semiconductor substrate, followed by forming an insulating film on the entire surface to fill at least the groove. Then, a flattening treatment is applied at least once to remove the insulating film from the substrate surface such that the insulating film is left unremoved only within the groove. In place of a wet etching treatment, a mirror-polishing method is employed for the last flattening treatment.

摘要翻译： 公开了通过STI（浅沟槽隔离）方法形成元件隔离绝缘膜的方法，其可有效地防止在元件隔离绝缘膜的边缘中形成凹部，从而减少处理步骤的数量，并且还 允许以高产率促进元件隔离绝缘膜的形成。 在形成元件隔离绝缘膜时，在半导体衬底的表面区域中形成沟槽，然后在整个表面上形成绝缘膜以至少填充沟槽。 然后，平坦化处理至少施加一次以从基板表面去除绝缘膜，使得绝缘膜仅在沟槽内不被移除。 代替湿蚀刻处理，最后的平坦化处理采用镜面抛光方法。

公开(公告)号：US06222722B1

公开(公告)日：2001-04-24

申请号：US09283280

申请日：1999-04-01

申请人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

发明人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

IPC分类号： H01G4008

CPC分类号： H01L28/82 ,  H01L27/10814 ,  H01L28/84 ,  H01L28/86 ,  H01L28/87 ,  H01L28/90 ,  H01L28/91

摘要： This invention provides a capacitor including a metal lower electrode having an undulated shape and an improved electrode area, and a method of manufacturing the same. A capacitor for data storage is formed on a semiconductor substrate (not shown) via an insulating interlayer having a contact plug. The capacitor has a lower electrode whose inner and outer surfaces are rough or undulated such that one surface has a shape conforming to the shape of the other surface, a dielectric film formed to cover the surfaces of the lower electrode, and an upper electrode formed to cover the lower electrode via the dielectric film. The lower electrode has a cylindrical shape with an open upper end. The lower electrode is connected to a cell transistor through the contact plug. The lower electrode is formed from a metal or a metal oxide.

公开(公告)号：US06198122B1

公开(公告)日：2001-03-06

申请号：US09025908

申请日：1998-02-19

申请人： Mariko Habu ,  Yusuke Kohyama ,  Toru Ozaki ,  Keiji Hosotani

发明人： Mariko Habu ,  Yusuke Kohyama ,  Toru Ozaki ,  Keiji Hosotani

IPC分类号： H01L27108

CPC分类号： H01L27/10894 ,  H01L27/10852

摘要： A semiconductor memory includes a semiconductor substrate, a memory cell portion formed on the substrate and including stacked capacitors formed on the substrate, each having a storage electrode formed on a bottom surface of a recess in an insulating layer, a capacitor insulating film formed on the storage electrode, and a plate electrode formed on the capacitor insulating film and lower than an upper edge of the recess, and a first multilayered interconnecting layer having an interconnecting layer including a plate interconnection connected to the plate electrode, and a peripheral circuit portion formed adjacent to the memory cell portion on the substrate and comprising a second multilayered interconnecting layer. The plate interconnection includes a portion so formed as to bury the recess and connected to the plate electrode, and the second multilayered interconnecting layer includes an interconnecting layer having an upper surface substantially leveled with an upper surface of the interconnecting layer including the plate interconnection of the first multilayered interconnecting layer.

摘要翻译： 半导体存储器包括半导体衬底，形成在衬底上的存储单元部分，并且包括形成在衬底上的叠层电容器，每个存储电极形成在绝缘层凹部的底表面上的存储电极，形成在绝缘层上的电容器绝缘膜 存储电极和形成在电容器绝缘膜上并低于凹部的上边缘的平板电极，以及具有互连层的第一多层互连层，所述互连层包括连接到平板电极的板状互连层，以及形成在邻接 到基板上的存储单元部分并且包括第二多层互连层。 板互连包括形成为埋入凹部并连接到平板电极的部分，并且第二多层互连层包括互连层，该互连层具有基本上与互连层的上表面大致平齐的互连层，包括互连层的板互连 第一多层互连层。

公开(公告)号：US06197675B1

公开(公告)日：2001-03-06

申请号：US09456990

申请日：1999-12-07

申请人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

发明人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

IPC分类号： H01L2144

CPC分类号： H01L27/10844 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/10852

摘要： A semiconductor memory device comprises a semiconductor substrate, a first conducting layer formed above the main surface of the semiconductor substrate, a second conducting layer formed above the first conducting layer through a first insulating layer and connected to the first conducting layer through a first via-conductor formed in a first contact hole formed in the first insulating layer, and a third conducting layer formed beneath the second conducting layer through a second insulating layer and connected to the second conducting layer through a second via-conductor formed in a second contact hole formed in the second insulating layer, in which an angle formed by a tangent to an inner wall of the first contact hole and a normal to the first conducting layer at a portion of the first conducting layer at which the first contact hole is in contact with the first conducting layer, is larger than an angle formed by a tangent to an inner wall of the second contact hole and a normal to the third conducting layer at a portion of the third conducting layer at which the second contact hole is in contact with the third conducting layer. By virtue of this structure, it is possible to avoid influence of electrical potential variation upon the first conducting layer in the manufacturing process.

摘要翻译： 半导体存储器件包括半导体衬底，形成在半导体衬底的主表面上的第一导电层，通过第一绝缘层形成在第一导电层上方的第二导电层，并通过第一通孔连接到第一导电层， 导体，形成在形成在第一绝缘层中的第一接触孔中，以及第三导电层，其通过第二绝缘层形成在第二导电层的下方，并通过形成在形成的第二接触孔中的第二通孔导体连接到第二导电层 在所述第二绝缘层中，所述第一接触孔与所述第一接触孔的内壁的切线形成的角度与所述第一导电层的所述第一导电层的与所述第一导电层接触的部分的垂直方向 第一导电层大于由与第二接触孔的内壁的切线形成的角度，并且与由垂直于第二接触孔的法线成正比 在第三导电层的第二接触孔与第三导电层接触的部分处的第三导电层。 由于这种结构，在制造过程中可以避免电势变化对第一导电层的影响。