公开(公告)号：US5345316A

公开(公告)日：1994-09-06

申请号：US978083

申请日：1992-11-17

申请人： Tohru Ozaki ,  Hitoshi Horie ,  Hideyuki Shirai

发明人： Tohru Ozaki ,  Hitoshi Horie ,  Hideyuki Shirai

IPC分类号： H04N1/413 ,  G06T9/00 ,  H04N1/411 ,  H04N1/417 ,  H04N1/419 ,  H04N1/41 ,  H04N1/40

CPC分类号： H04N1/4175 ,  H04N1/411

摘要： An image data encoding/decoding apparatus having an encoder and decoder for processing image data such as facsimile data, in which two different streams of image data can be encoded concurrently by using a single encoding circuit section, and two different streams of encoded data can be decoded concurrently using a single decoding section. The encoded data obtained for each scan line portion of the image data are modified, if necessary, to be converted to an integral number of fixed-size amounts of data such as bytes, for subsequent storage in memory. During decoding processing, the encoded data line portions are restored to their respective original forms prior to decoding processing, by controlled operation of registers in which the encoded data are temporarily written in and then serially read out.

摘要翻译： 具有用于处理诸如传真数据的图像数据的编码器和解码器的图像数据编码/解码装置可以通过使用单个编码电路部分同时编码两个不同的图像数据流，以及两个不同的编码数据流可以是 使用单个解码部分同时解码。 如果需要，对图像数据的每个扫描线部分获得的编码数据进行修改，以将其转换成固定大小的诸如字节的数据量的整数，以便随后存储在存储器中。 在解码处理期间，编码数据线部分在解码处理之前通过被编码数据被暂时写入然后被串行读出的寄存器的受控操作被恢复到它们各自的原始形式。

公开(公告)号：US5087969A

公开(公告)日：1992-02-11

申请号：US554365

申请日：1990-07-19

申请人： Hiroshi Kamada ,  Tohru Ozaki

发明人： Hiroshi Kamada ,  Tohru Ozaki

IPC分类号： G05D1/02

CPC分类号： G05D1/0246 ,  G05D1/0221 ,  G05D1/0234 ,  G05D2201/0213 ,  Y10S706/90

摘要： A system for controlling an unmanned vehicle by detection of a guide line based on a picture image picked up by a camera on the vehicle, including a parameter (.rho., .theta.) deriving unit for deriving parameters (.rho., .theta.) of point extracted from a picture image picked up by a camera, and a maximum density parameter detection unit for integrating the densities of parameters derived by the parameter deriving unit and determining the maximum density parameter from the integrated densities of the parameters. The maximum density parameter is determined from the parameter derived by the parameter deriving unit, for the parameter area having at the center thereof the parameter estimated from the maximum density parameter, and the detected maximum density parameter is decided as the parameter of said guide line. The determination of steered amount by a fuzzy inference can be used.

公开(公告)号：US4791678A

公开(公告)日：1988-12-13

申请号：US161274

申请日：1988-02-22

申请人： Hiromichi Iwase ,  Shigeru Sasaki ,  Toshiyuki Gotoh ,  Takashi Toriu ,  Tohru Ozaki

发明人： Hiromichi Iwase ,  Shigeru Sasaki ,  Toshiyuki Gotoh ,  Takashi Toriu ,  Tohru Ozaki

IPC分类号： G06T5/00 ,  G06K9/36 ,  G06K9/80 ,  G06T5/20 ,  G06T7/00 ,  G06K9/40

CPC分类号： G06T5/20

摘要： An image processing system mainly used in an image verification system for detecting and correcting distortion of an input image includes the following devices; an image memory for storing a digitized image before, during, and after correction, a working memory for temporarily storing intermediate data of the image on correction, density level extension devices for extending the density level or gradation of the image by repeatedly reading out the contents of the image memory and the working memory by using a matrix window containing picture elements of the image, a density slope detection device for detecting the extended density level and calculating a density slope or gradient by using the matrix window, and a correction device for correcting density distribution and line width of the image based on the extended density level and the calculated density slope.

摘要翻译： 主要用于检测和校正输入图像失真的图像验证系统中的图像处理系统包括以下装置; 用于在校正之前，之中和之后存储数字化图像的图像存储器，用于临时存储修正图像的中间数据的工作存储器，用于通过重复读出内容来扩展图像的浓度级或灰度级的浓度级扩展装置 通过使用包含图像的图像的矩阵窗口的图像存储器和工作存储器，密度斜率检测装置，用于通过使用矩阵窗口来检测扩展密度级别并计算密度斜率或梯度;以及校正装置， 基于扩展密度水平和计算密度斜率的图像的密度分布和线宽。

公开(公告)号：US08476693B2

公开(公告)日：2013-07-02

申请号：US13050297

申请日：2011-03-17

申请人： Takayuki Toba ,  Tohru Ozaki

发明人： Takayuki Toba ,  Tohru Ozaki

IPC分类号： H01L29/788

CPC分类号： H01L27/11524 ,  H01L27/11534 ,  H01L29/66825

摘要： In one embodiment, a nonvolatile semiconductor memory includes a memory cell array, a first silicon nitride film and a second silicon nitride film. The memory cell array includes NAND cell units. Each of the NAND cell units has memory cell transistors, a source-side select gate transistor and a drain-side select gate transistor. The source-side select gate transistors is disposed in such a manner as to face each other and the drain-side select gate transistors is disposed in such a manner as to face each other. The first silicon nitride film is present in a region between the source-side select gate transistors and is disposed at a position lowest from the upper surface of the semiconductor substrate. The second silicon nitride film is formed in a region between the drain-side select gate transistors and is disposed at a position lowest from the upper surface of the semiconductor substrate.

摘要翻译： 在一个实施例中，非易失性半导体存储器包括存储单元阵列，第一氮化硅膜和第二氮化硅膜。 存储单元阵列包括NAND单元单元。 每个NAND单元单元具有存储单元晶体管，源极选择栅极晶体管和漏极侧选择栅极晶体管。 源极侧选择栅极晶体管以彼此面对的方式设置，并且漏极侧选择栅极晶体管以彼此面对的方式设置。 第一氮化硅膜存在于源极选择栅晶体管之间的区域中，并且设置在从半导体衬底的上表面最低的位置。 第二氮化硅膜形成在漏极侧选择栅晶体管之间的区域中，并且设置在从半导体衬底的上表面最低的位置。

公开(公告)号：US06759251B2

公开(公告)日：2004-07-06

申请号：US10320524

申请日：2002-12-17

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L2100

CPC分类号： H01L27/11502 ,  H01L21/76838 ,  H01L28/55

摘要： A semiconductor device having ferroelectric memory cells has memory cell transistors each including first and second source/drain regions. Plug electrodes are formed in contact with the first and second source/drain regions, respectively. A ferroelectric capacitor is formed on the plug electrode connected to the first source/drain region. The ferroelectric capacitor includes a first lower electrode formed on the plug electrode, a ferroelectric film formed on the first lower electrode, and an upper electrode formed on the ferroelectric film. A second lower electrode is formed on the plug electrode connected to the second source/drain region. Wiring is formed to connect the upper electrode to the corresponding second lower electrode.

摘要翻译： 具有铁电存储单元的半导体器件具有各自包括第一和第二源/漏区的存储单元晶体管。 插塞电极分别形成为与第一和第二源极/漏极区域接触。 在与第一源/漏区连接的插头电极上形成铁电电容器。 铁电电容器包括形成在插头电极上的第一下电极，形成在第一下电极上的铁电膜和形成在铁电体膜上的上电极。 在与第二源/漏区连接的插头电极上形成第二下电极。 形成布线以将上电极连接到相应的第二下电极。

公开(公告)号：US06448618B1

公开(公告)日：2002-09-10

申请号：US09640707

申请日：2000-08-18

申请人： Satoshi Inaba ,  Tohru Ozaki ,  Yusuke Kohyama ,  Kazumesa Sunouchi

发明人： Satoshi Inaba ,  Tohru Ozaki ,  Yusuke Kohyama ,  Kazumesa Sunouchi

IPC分类号： H01L27108

CPC分类号： H01L27/10844 ,  H01L27/105 ,  H01L27/108 ,  Y10S257/90

摘要： In a DRAM, a plurality of first MOSFETs are formed in a cell region on a semiconductor substrate based on the minimum design rule, and a first gate side-wall having a side-wall insulation film is formed on the side-wall portion of a first gate electrode of each of the first MOSFETs. At least one second MOSFET is formed in a peripheral circuit region on the semiconductor substrate, and a second gate side-wall having side-wall insulation films is formed on the side-wall portion of a second gate electrode of the second MOSFET. Both the first MOSFETs, which is capable of forming a fine contact hole self-aligned with the first gate electrode, and the second MOSFET, which is capable of sufficiently mitigating the parasitic resistance while suppressing the short channel effect, can be formed on the same substrate.

摘要翻译： 在DRAM中，基于最小设计规则，在半导体衬底上的单元区域中形成多个第一MOSFET，并且在侧壁部分上形成具有侧壁绝缘膜的第一栅极侧壁 每个第一MOSFET的第一栅电极。 在半导体衬底上的外围电路区域中形成至少一个第二MOSFET，并且在第二MOSFET的第二栅电极的侧壁部分上形成具有侧壁绝缘膜的第二栅极侧壁。 能够形成与第一栅电极自对准的精细接触孔的第一MOSFET和能够在抑制短沟道效应的同时充分减轻寄生电阻的第二MOSFET同时形成 基质。

公开(公告)号：US5899739A

公开(公告)日：1999-05-04

申请号：US714405

申请日：1996-09-16

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L27/04 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/44

CPC分类号： H01L27/10852 ,  H01L21/76831 ,  H01L21/76897 ,  H01L27/10861

摘要： A method of manufacturing a semiconductor device. First, a plurality of wires are arranged in parallel to one another, on a semiconductor substrate. Then, insulating films of a first group are formed on tops of the wires, respectively. Next, second insulating films of a second group are formed on sides of the wires, respectively. Further, among the wires there are formed insulating films of a third group which have upper surfaces located at a level not higher than upper surfaces of the insulating films of the second group. Thereafter, contact holes are formed by subjecting the insulating films of the third group to selectively etching. Finally, the contact holes are filled with electrically conductive material.

公开(公告)号：US5753526A

公开(公告)日：1998-05-19

申请号：US603069

申请日：1996-02-20

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L27/10864

摘要： A method of manufacturing process of a semiconductor device, including the steps of forming a plurality of first trenches in a checkered configuration in a substrate, each of the first trenches having an opening; introducing a first conductivity type impurity from a surface of the substrate so as to form a first conductivity type well in a upper portion of the substrate; forming a capacitor insulating film on a surface of each of the first trenches and burying a storage electrode in each of the first trenches so as to form a trench capacitor in each of the first trenches; burying a first silicon film on each of the storage electrodes of the trench capacitors in the first trenches, etching back each of portions of the first silicon film and removing each of portions of the capacitor insulating films so as to expose portions of side surfaces of the first conductivity type well facing the first trenches; burying a second silicon film doped with a second conductivity type impurity in each of concave portions surrounded by the first silicon films and exposing side surfaces of the first conductivity type well facing the first trenches, and introducing second conductivity type impurities to the first conductivity type well so as to form source regions; and burying a first insulation material on the first and second silicon films in each of the first trenches.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在衬底中形成多个第一沟槽，每个第一沟槽均具有开口; 从所述基板的表面引入第一导电型杂质，以在所述基板的上部形成良好的第一导电型; 在每个第一沟槽的表面上形成电容器绝缘膜，并在每个第一沟槽中埋设存储电极，以在每个第一沟槽中形成沟槽电容器; 在第一沟槽中的沟槽电容器的每个存储电极上埋入第一硅膜，蚀刻第一硅膜的每个部分并去除电容器绝缘膜的每个部分，以暴露出第一硅膜的侧表面的部分 第一导电类型井面对第一沟槽; 在由第一硅膜围绕的每个凹部中埋入掺杂有第二导电类型杂质的第二硅膜，并暴露出面向第一沟槽的第一导电类型的侧表面，并将第二导电类型杂质引入第一导电类型阱 以形成源区; 以及在所述第一沟槽的每一个中的第一和第二硅膜上埋设第一绝缘材料。

公开(公告)号：US5629887A

公开(公告)日：1997-05-13

申请号：US429638

申请日：1995-04-27

申请人： Hiroaki Nakano ,  Daisaburo Takashima ,  Tohru Ozaki

发明人： Hiroaki Nakano ,  Daisaburo Takashima ,  Tohru Ozaki

IPC分类号： G11C11/4097 ,  H01L23/522 ,  H01L27/108 ,  G11C5/02 ,  G11C5/06

CPC分类号： G11C11/4097 ,  H01L23/5222 ,  H01L27/10805 ,  H01L2924/0002

摘要： A dynamic semiconductor memory device according to the present invention, comprises a plurality of first bit lines, a plurality of second bit lines which are partially laminated above the first bit lines and, together with the first bit lines, form bit-line pairs to build a folded bit-line structure, a plurality of word lines arranged so as to cross the first bit lines and the second bit lines, and at least one memory cell array in which a plurality of memory cells connected to the first bit lines and the second bit lines are arranged in a matrix, wherein the memory cell array includes a plurality of first areas in which a plurality of memory cells are arranged, and a plurality of second memory areas which are arranged so as to alternate with the first areas and contain no memory cell, and the second memory areas include areas where the first bit lines of the specified number of the bit-line pairs are connected to the second bit lines and the second bit lines are connected to the first bit lines.

摘要翻译： 根据本发明的动态半导体存储器件包括多个第一位线，多个第二位线，其部分地层叠在第一位线上方，并与第一位线一起形成位线对以构建 折叠的位线结构，布置成跨越第一位线和第二位线的多个字线，以及至少一个存储单元阵列，其中多个存储单元连接到第一位线和第二位线 位线布置成矩阵，其中存储单元阵列包括多个第一区域，其中布置有多个存储单元;以及多个第二存储区域，其布置成与第一区域交替并且不包含 存储单元，并且第二存储器区域包括指定数量的位线对的第一位线连接到第二位线的区域，并且第二位线连接到第一位线 位线。

公开(公告)号：US5459793A

公开(公告)日：1995-10-17

申请号：US939837

申请日：1992-09-02

申请人： Satoshi Naoi ,  Tohru Ozaki

发明人： Satoshi Naoi ,  Tohru Ozaki

IPC分类号： A63B69/36 ,  G01S3/786 ,  G06T1/00 ,  G06T7/00 ,  G06T7/20 ,  H04N5/262 ,  H04N9/74 ,  G06K9/00

CPC分类号： H04N9/74 ,  G01S3/7864 ,  G06T7/20 ,  H04N5/2625

摘要： A motion analysis system utilizing an image processing technique includes a color marker attached to an object which is to be analyzed. Each color marker has a high directivity reflective member on a surface thereof, and the reflection member reflects light having a particular wavelength. A light source generates light for irradiation onto the color marker. A color TV camera aligned in roughly the same direction as that of the light source receives reflected light from the color marker and outputs a color image. A color extraction unit connected to the TV camera, extracts only a particular color from the color image produced by the TV camera. An area calculation unit connected to the color extraction unit, calculates the area of the particular color extracted by the color extraction unit. A diaphragm adjustment unit connected between the TV camera and the area calculation unit adjusts the diaphragm of the TV camera so as to make the area calculated by the area calculation unit equivalent to the actual color area of the color marker and a center of gravity calculation unit connected to the area calculation unit, calculates a position of the center of gravity of the particular color based on the area calculated by the area calculation unit.

摘要翻译： 利用图像处理技术的运动分析系统包括附着到待分析对象的颜色标记。 每个颜色标记在其表面上具有高方向性反射构件，并且反射构件反射具有特定波长的光。 光源产生用于照射到颜色标记上的光。 以与光源大致相同的方向排列的彩色电视摄像机接收来自颜色标记的反射光并输出彩色图像。 连接到TV摄像机的彩色提取单元，仅从TV摄像机产生的彩色图像中提取特定的颜色。 连接到颜色提取单元的区域计算单元计算由颜色提取单元提取的特定颜色的面积。 连接在TV摄像机和区域计算单元之间的光阑调节单元调节TV摄像机的光阑，以使得由区域计算单元计算的面积等于彩色标记的实际颜色面积和重心计算单元 连接到区域计算单元，基于由区域计算单元计算出的面积来计算特定颜色的重心位置。