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    Semiconductor device and method for manufacturing the same
    1.
    发明授权
    Semiconductor device and method for manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06448618B1

    公开(公告)日：2002-09-10

    申请号：US09640707

    申请日：2000-08-18

    申请人： Satoshi Inaba ,  Tohru Ozaki ,  Yusuke Kohyama ,  Kazumesa Sunouchi

    发明人： Satoshi Inaba ,  Tohru Ozaki ,  Yusuke Kohyama ,  Kazumesa Sunouchi

    IPC分类号： H01L27108

    CPC分类号： H01L27/10844 ,  H01L27/105 ,  H01L27/108 ,  Y10S257/90

    摘要： In a DRAM, a plurality of first MOSFETs are formed in a cell region on a semiconductor substrate based on the minimum design rule, and a first gate side-wall having a side-wall insulation film is formed on the side-wall portion of a first gate electrode of each of the first MOSFETs. At least one second MOSFET is formed in a peripheral circuit region on the semiconductor substrate, and a second gate side-wall having side-wall insulation films is formed on the side-wall portion of a second gate electrode of the second MOSFET. Both the first MOSFETs, which is capable of forming a fine contact hole self-aligned with the first gate electrode, and the second MOSFET, which is capable of sufficiently mitigating the parasitic resistance while suppressing the short channel effect, can be formed on the same substrate.

    摘要翻译： 在DRAM中，基于最小设计规则，在半导体衬底上的单元区域中形成多个第一MOSFET，并且在侧壁部分上形成具有侧壁绝缘膜的第一栅极侧壁 每个第一MOSFET的第一栅电极。 在半导体衬底上的外围电路区域中形成至少一个第二MOSFET，并且在第二MOSFET的第二栅电极的侧壁部分上形成具有侧壁绝缘膜的第二栅极侧壁。 能够形成与第一栅电极自对准的精细接触孔的第一MOSFET和能够在抑制短沟道效应的同时充分减轻寄生电阻的第二MOSFET同时形成 基质。

    Structure of a capacitor section of a dynamic random-access memory
    3.
    发明授权
    Structure of a capacitor section of a dynamic random-access memory 失效
    动态随机存取存储器的电容器部分的结构

    公开(公告)号：US06303429B1

    公开(公告)日：2001-10-16

    申请号：US09676084

    申请日：2000-10-02

    申请人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

    发明人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

    IPC分类号： H01L218242

    CPC分类号： H01L27/10885 ,  H01L27/10852 ,  H01L27/10873 ,  H01L28/91

    摘要： Capacitors are formed in the trenches made in an interlayer insulator made of silicon oxide. An insulating film (e.g., a silicon nitride film) is provided on the sides of each trench of the interlayer insulator. A storage electrode made of ruthenium or the like is provided in each trench of the interlayer insulator. A capacitor insulating film made of BSTO or the like is formed on the storage electrode. A plate electrode made of ruthenium or the like is formed on the capacitor insulating film. The plate electrode is common to all capacitors provided. Any two adjacent capacitors are electrically isolated by the interlayer insulator and the insulating film provided on the sides of the trenches of the interlayer insulator.

    摘要翻译： 电容器形成在由氧化硅制成的层间绝缘体中制成的沟槽中。 绝缘膜（例如，氮化硅膜）设置在层间绝缘体的每个沟槽的侧面上。 在层间绝缘体的每个沟槽中设置由钌等制成的存储电极。 在存储电极上形成由BSTO等构成的电容绝缘膜。 在电容器绝缘膜上形成由钌等制成的平板电极。 平板电极对所有提供的电容器是共同的。 任何两个相邻的电容器通过层间绝缘体和设置在层间绝缘体的沟槽的侧面上的绝缘膜电隔离。

    Semiconductor device adopting a self-aligned contact structure and method for manufacturing a semiconductor memory device
    4.
    发明授权
    Semiconductor device adopting a self-aligned contact structure and method for manufacturing a semiconductor memory device 有权
    采用自对准接触结构的半导体器件和半导体存储器件的制造方法

    公开(公告)号：US6104052A

    公开(公告)日：2000-08-15

    申请号：US273573

    申请日：1999-03-22

    申请人： Tohru Ozaki ,  Yusuke Kohyama

    发明人： Tohru Ozaki ,  Yusuke Kohyama

    IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01L29/72

    CPC分类号： H01L27/10894 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/91

    摘要： In a DRAM adopting a self-aligned contact structure, an opening portion of predetermined size is formed in advance in an insulation film which surrounds an on-field gate electrode formed on an element isolating insulation film. The on-field gate electrode contacts a gate contact through the opening portion. A contact hole for the gate contact can thus be formed in self-alignment as can be the contact holes for a bit-line contact and an active contact. Consequently, the contact hole for the gate contact reaching the on-field gate can be formed simultaneously with the contact holes for the bit-line contact and active contact, thereby greatly reducing the number of manufacturing steps.

    摘要翻译： 在采用自对准接触结构的DRAM中，预先形成围绕形成在元件隔离绝缘膜上的场上栅电极的绝缘膜中的预定尺寸的开口部分。 场电极电极通过开口部分接触栅极接触。 因此，用于栅极接触的接触孔可以自对准地形成，就像位线接触和有源触点的接触孔一样。 因此，到达栅极栅极的接触孔可以与用于位线接触和有源接触的接触孔同时形成，从而大大减少了制造步骤的数量。

    Structure of a capacitor section of a dynamic random-access memory
    5.
    发明授权
    Structure of a capacitor section of a dynamic random-access memory 失效

    公开(公告)号：US06635933B2

    公开(公告)日：2003-10-21

    申请号：US09953306

    申请日：2001-09-17

    申请人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

    发明人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

    IPC分类号： H01L2976

    CPC分类号： H01L27/10885 ,  H01L27/10852 ,  H01L27/10873 ,  H01L28/91

    摘要： Capacitors are formed in the trenches made in an interlayer insulator made of silicon oxide. An insulating film (e.g., a silicon nitride film) is provided on the sides of each trench of the interlayer insulator. A storage electrode made of ruthenium or the like is provided in each trench of the interlayer insulator. A capacitor insulating film made of BSTO or the like is formed on the storage electrode. A plate electrode made of ruthenium or the like is formed on the capacitor insulating film. The plate electrode is common to all capacitors provided. Any two adjacent capacitors are electrically isolated by the interlayer insulator and the insulating film provided on the sides of the trenches of the interlayer insulator.

    Reduction of short-circuiting between contacts at or near a tensile-compressive boundary
    6.
    发明授权
    Reduction of short-circuiting between contacts at or near a tensile-compressive boundary 失效
    在拉伸 - 压缩边界处或附近减少接触之间的短路

    公开(公告)号：US07514752B2

    公开(公告)日：2009-04-07

    申请号：US11211604

    申请日：2005-08-26

    申请人： Yusuke Kohyama

    发明人： Yusuke Kohyama

    IPC分类号： H01L29/76

    CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823871

    摘要： Methods and apparatus are described that reduce the possibility that unintended subway short-circuits will occur between contacts of different potentials along the boundary between tensile and compressive liners (the T-C boundary). This may be done without unduly increasing the size of the semiconductor device, or even increasing the size at all over previous designs. For example, simply by adjusting the layout of the device, the contacts of two different common gates may be offset in opposing directions relative to the T-C boundary. Or, by forming a T-C boundary having a zigzag or other similar pattern, the contacts may be arranged even closer together while still reducing the likelihood of short-circuiting subways forming. Such layout adjustments do not otherwise require any additional steps or cost.

    摘要翻译： 描述了减少在拉伸和压缩衬里（T-C边界）之间的边界处的不同电位的触点之间发生意外的地铁短路的可能性。 这可以在不过度增加半导体器件的尺寸的情况下进行，或者甚至在以前的设计中增加尺寸。 例如，简单地通过调整装置的布局，两个不同公共栅极的触点可以相对于T-C边界相反的方向偏移。 或者，通过形成具有锯齿形或其他类似图案的T-C边界，可以将触点设置得更靠近在一起，同时仍然减少了地铁短路形成的可能性。 这样的布局调整不需要额外的步骤或成本。

    Method of manufacturing semiconductor device
    9.
    发明授权
    Method of manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06225230B1

    公开(公告)日：2001-05-01

    申请号：US08861736

    申请日：1997-05-22

    申请人： Hiroyuki Nitta ,  Yusuke Kohyama

    发明人： Hiroyuki Nitta ,  Yusuke Kohyama

    IPC分类号： H01L2100

    CPC分类号： H01L21/76229

    摘要： Disclosed is a method of forming an element isolation insulating film by STI (shallow trench isolation) method, which permits effectively preventing a concave portion from being formed in an edge of the element isolation insulating film, permits decreasing the number of treating steps, and also permits facilitating the formation of the element isolation insulating film with a high yield. In forming the element isolation insulating film, a groove is formed in a surface region of a semiconductor substrate, followed by forming an insulating film on the entire surface to fill at least the groove. Then, a flattening treatment is applied at least once to remove the insulating film from the substrate surface such that the insulating film is left unremoved only within the groove. In place of a wet etching treatment, a mirror-polishing method is employed for the last flattening treatment.

    摘要翻译： 公开了通过STI（浅沟槽隔离）方法形成元件隔离绝缘膜的方法，其可有效地防止在元件隔离绝缘膜的边缘中形成凹部，从而减少处理步骤的数量，并且还 允许以高产率促进元件隔离绝缘膜的形成。 在形成元件隔离绝缘膜时，在半导体衬底的表面区域中形成沟槽，然后在整个表面上形成绝缘膜以至少填充沟槽。 然后，平坦化处理至少施加一次以从基板表面去除绝缘膜，使得绝缘膜仅在沟槽内不被移除。 代替湿蚀刻处理，最后的平坦化处理采用镜面抛光方法。

    Storage capacitor having undulated lower electrode for a semiconductor device
    10.
    发明授权
    Storage capacitor having undulated lower electrode for a semiconductor device 失效

    公开(公告)号：US06222722B1

    公开(公告)日：2001-04-24

    申请号：US09283280

    申请日：1999-04-01

    申请人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

    发明人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

    IPC分类号： H01G4008

    CPC分类号： H01L28/82 ,  H01L27/10814 ,  H01L28/84 ,  H01L28/86 ,  H01L28/87 ,  H01L28/90 ,  H01L28/91

    摘要： This invention provides a capacitor including a metal lower electrode having an undulated shape and an improved electrode area, and a method of manufacturing the same. A capacitor for data storage is formed on a semiconductor substrate (not shown) via an insulating interlayer having a contact plug. The capacitor has a lower electrode whose inner and outer surfaces are rough or undulated such that one surface has a shape conforming to the shape of the other surface, a dielectric film formed to cover the surfaces of the lower electrode, and an upper electrode formed to cover the lower electrode via the dielectric film. The lower electrode has a cylindrical shape with an open upper end. The lower electrode is connected to a cell transistor through the contact plug. The lower electrode is formed from a metal or a metal oxide.