公开(公告)号：US06448618B1

公开(公告)日：2002-09-10

申请号：US09640707

申请日：2000-08-18

申请人： Satoshi Inaba ,  Tohru Ozaki ,  Yusuke Kohyama ,  Kazumesa Sunouchi

发明人： Satoshi Inaba ,  Tohru Ozaki ,  Yusuke Kohyama ,  Kazumesa Sunouchi

IPC分类号： H01L27108

CPC分类号： H01L27/10844 ,  H01L27/105 ,  H01L27/108 ,  Y10S257/90

摘要： In a DRAM, a plurality of first MOSFETs are formed in a cell region on a semiconductor substrate based on the minimum design rule, and a first gate side-wall having a side-wall insulation film is formed on the side-wall portion of a first gate electrode of each of the first MOSFETs. At least one second MOSFET is formed in a peripheral circuit region on the semiconductor substrate, and a second gate side-wall having side-wall insulation films is formed on the side-wall portion of a second gate electrode of the second MOSFET. Both the first MOSFETs, which is capable of forming a fine contact hole self-aligned with the first gate electrode, and the second MOSFET, which is capable of sufficiently mitigating the parasitic resistance while suppressing the short channel effect, can be formed on the same substrate.

摘要翻译： 在DRAM中，基于最小设计规则，在半导体衬底上的单元区域中形成多个第一MOSFET，并且在侧壁部分上形成具有侧壁绝缘膜的第一栅极侧壁 每个第一MOSFET的第一栅电极。 在半导体衬底上的外围电路区域中形成至少一个第二MOSFET，并且在第二MOSFET的第二栅电极的侧壁部分上形成具有侧壁绝缘膜的第二栅极侧壁。 能够形成与第一栅电极自对准的精细接触孔的第一MOSFET和能够在抑制短沟道效应的同时充分减轻寄生电阻的第二MOSFET同时形成 基质。

公开(公告)号：US6153476A

公开(公告)日：2000-11-28

申请号：US30127

申请日：1998-02-25

申请人： Satoshi Inaba ,  Tohru Ozaki ,  Yusuke Kohyama ,  Kazumasa Sunouchi

发明人： Satoshi Inaba ,  Tohru Ozaki ,  Yusuke Kohyama ,  Kazumasa Sunouchi

IPC分类号： H01L21/8234 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/088 ,  H01L27/105 ,  H01L27/108 ,  H01L21/336

CPC分类号： H01L27/10844 ,  H01L27/105 ,  H01L27/108 ,  Y10S257/90

摘要： In a DRAM, a plurality of first MOSFETs are formed in a cell region on a semiconductor substrate based on the minimum design rule, and a first gate side-wall having a side-wall insulation film is formed on the side-wall portion of a first gate electrode of each of the first MOSFETs. At least one second MOSFET is formed in a peripheral circuit region on the semiconductor substrate, and a second gate side-wall having side-wall insulation films is formed on the side-wall portion of a second gate electrode of the second MOSFET. Both the first MOSFETs, which is capable of forming a fine contact hole self-aligned with the first gate electrode, and the second MOSFET, which is capable of sufficiently mitigating the parasitic resistance while suppressing the short channel effect, can be formed on the same substrate.

公开(公告)号：US5698869A

公开(公告)日：1997-12-16

申请号：US527515

申请日：1995-09-13

申请人： Makoto Yoshimi ,  Satoshi Inaba ,  Atsushi Murakoshi ,  Mamoru Terauchi ,  Naoyuki Shigyo ,  Yoshiaki Matsushita ,  Masami Aoki ,  Takeshi Hamamoto ,  Yutaka Ishibashi ,  Tohru Ozaki ,  Hitomi Kawaguchiya ,  Kazuya Matsuzawa ,  Osamu Arisumi ,  Akira Nishiyama

发明人： Makoto Yoshimi ,  Satoshi Inaba ,  Atsushi Murakoshi ,  Mamoru Terauchi ,  Naoyuki Shigyo ,  Yoshiaki Matsushita ,  Masami Aoki ,  Takeshi Hamamoto ,  Yutaka Ishibashi ,  Tohru Ozaki ,  Hitomi Kawaguchiya ,  Kazuya Matsuzawa ,  Osamu Arisumi ,  Akira Nishiyama

IPC分类号： H01L21/336 ,  H01L27/12 ,  H01L29/786 ,  H01L31/072

CPC分类号： H01L29/66666 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78681

摘要： A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Si.sub.x Ge.sub.1-x, Si.sub.x Sn.sub.1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed. Further the structure that the influences of the crystal defects to the transistor or memory characteristics such as the leakage current can be suppressed, even if the crystal defects are generated, are also proposed.

摘要翻译： 提供半导体器件的结构及其制造方法，其中可以减小漏电流，同时改善诸如MOSFET，MOSSIT和MISFET的绝缘栅晶体管的漏极击穿电压，以及保持特性 可以提高诸如使用这些晶体管的DRAM作为开关晶体管的存储单元，并且还可以提高传输栅极中的栅极氧化膜的可靠性。 更具体地，在SOI.IG器件中的源极区域或漏极区域的内部形成诸如SixGe1-x，SixSn1-x，PbS的窄带隙半导体区域。 通过选择SOI膜中的窄带隙半导体区域的位置和/或摩尔分数，或者选择一种杂质元素来补偿由于窄带隙半导体区域引起的晶格失配，可以抑制晶体缺陷的产生 。 此外，即使产生晶体缺陷，也可以抑制晶体缺陷对晶体管的影响或漏电流等存储特性的结构。

公开(公告)号：US08481908B2

公开(公告)日：2013-07-09

申请号：US13038691

申请日：2011-03-02

申请人： Satoshi Inaba

发明人： Satoshi Inaba

IPC分类号： H01L27/00 ,  H01L31/00 ,  H01J40/14 ,  H04N3/14

CPC分类号： H01L27/14647 ,  H01L27/1461

摘要： According to one embodiments, a transparent reference electrode is provided to be sandwiched between a red-detecting photoelectric conversion film and a green-detecting photoelectric conversion film, a first transparent driving electrode is provided to face the transparent reference electrode with the green-detecting photoelectric conversion film therebetween, a second transparent driving electrode is provided to face the transparent reference electrode with the red-detecting photoelectric conversion film therebetween, and a blue-detecting photoelectric conversion film is provided below the red-detecting photoelectric conversion film and performs blue detection.

摘要翻译： 根据一个实施例，提供透明参考电极以被夹在红色检测光电转换膜和绿色检测光电转换膜之间，设置第一透明驱动电极以与绿色检测光电 转换膜之间设置有第二透明驱动电极，其间具有红色检测光电转换膜而与透明参考电极相对，蓝色检测光电转换膜设置在红色检测光电转换膜的下方并执行蓝色检测。

公开(公告)号：US08368148B2

公开(公告)日：2013-02-05

申请号：US13176220

申请日：2011-07-05

申请人： Satoshi Inaba

发明人： Satoshi Inaba

IPC分类号： H01L27/092

CPC分类号： H01L27/0207 ,  G11C11/412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  Y10S257/903

摘要： A semiconductor device according to an aspect of the invention comprises an n-type FinFET which is provided on a semiconductor substrate and which includes a first fin, a first gate electrode crossing a channel region of the first fin via a gate insulating film in three dimensions, and contact regions provided at both end of the first fin, a p-type FinFET which is provided on the semiconductor substrate and which includes a second fin, a second gate electrode crossing a channel region of the second fin via a gate insulating film in three dimensions, and contact regions provided at both end of the second fin, wherein the n- and the p-type FinFET constitute an inverter circuit, and the fin width of the contact region of the p-type FinFET is greater than the fin width of the channel region of the n-type FinFET.

摘要翻译： 根据本发明的一个方面的半导体器件包括n型FinFET，其设置在半导体衬底上，并且包括第一鳍，第一栅电极，三维中经由栅极绝缘膜与第一鳍的沟道区交叉 以及设置在第一鳍片两端的接触区域，设置在半导体衬底上并包括第二鳍片的p型FinFET，经由栅极绝缘膜与第二鳍片的沟道区域交叉的第二栅电极， 三维尺寸和设置在第二鳍片两端的接触区域，其中n型和p型FinFET构成逆变器电路，并且p型FinFET的接触区域的鳍宽度大于翅片宽度 的n型FinFET的沟道区域。

公开(公告)号：US07795682B2

公开(公告)日：2010-09-14

申请号：US11700147

申请日：2007-01-31

申请人： Akio Kaneko ,  Atsushi Yagishita ,  Satoshi Inaba

发明人： Akio Kaneko ,  Atsushi Yagishita ,  Satoshi Inaba

IPC分类号： H01L29/786

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/6681 ,  H01L29/7843

摘要： The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.

摘要翻译： 本公开涉及一种制造半导体器件的方法，包括在绝缘层上形成由半导体材料制成的多个鳍片; 在所述多个翅片的侧面上形成栅极绝缘膜; 以及在所述栅极绝缘膜上形成栅电极，使得在与所述侧面垂直的方向上在所述多个翅片中的NMOSFET中使用的第一鳍片的侧面施加压缩应力， 在垂直于侧面的方向上，在多个翅片中的PMOSFET中使用的第二鳍片的侧面施加应力。

公开(公告)号：US07522445B2

公开(公告)日：2009-04-21

申请号：US11657130

申请日：2007-01-24

申请人： Satoshi Inaba

发明人： Satoshi Inaba

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/785

摘要： A semiconductor memory having a plurality of static random access memory cells, word lines, first and second bit lines orthogonal to the word lines, and threshold voltage control lines parallel to the word lines and each of the static random access memory cell includes the first and the second driver transistors, the first and the second load transistors, and the first and the second transfer transistors configured by Fin field effect transistors, and at least one of the Fin field effect transistors is configured by a separated-gate type double-gate field effect transistor comprising a first gate electrode and a second gate electrode and controlling a voltage for the first gate electrode to form a channel, and controlling a voltage for the second gate electrode to decrease a threshold voltage at the time of writing data.

摘要翻译： 具有多个静态随机存取存储器单元，字线，与字线正交的第一和第二位线的半导体存储器以及与字线平行的阈值电压控制线以及每个静态随机存取存储单元包括第一和 第二驱动晶体管，第一和第二负载晶体管以及由Fin场效应晶体管构成的第一和第二转移晶体管，并且Fin场效应晶体管中的至少一个由分离栅型双栅极场 所述第一效应晶体管包括第一栅电极和第二栅极，并且控制所述第一栅电极的电压以形成沟道，并且控制所述第二栅电极的电压以在写数据时降低阈值电压。

公开(公告)号：US07125779B2

公开(公告)日：2006-10-24

申请号：US10911596

申请日：2004-08-05

申请人： Satoshi Inaba

发明人： Satoshi Inaba

IPC分类号： H01L21/336

CPC分类号： H01L29/66553 ,  H01L21/28123 ,  H01L29/665 ,  H01L29/66621 ,  H01L29/7834

摘要： There is provided a MISFET which suppresses a short-channel effect in a deep submicron region and has a low parasitic resistance, a low parasitic capacitance, and a small drain junction leakage current. A shallow concave is formed in a channel forming portion and an extension region forming portion of a MISFET, shallow ion implantation for forming an extension region is performed to a bottom surface of the shallow concave. Deep ion implantation for forming a source/drain region is performed to a silicon substrate adjacent to the concave, and the position of a peak concentration of the shallow ion implantation is caused to coincide with the position of a peak concentration of the deep ion implantation, so that a MISFET which suppresses a short-channel effect and has a low source/drain parasitic resistance, a low source/drain parasitic capacitance, and a small drain junction leakage current generated by SALICIDE steps can be provided. The MISFET according to the invention is preferably used as a means for providing a semiconductor substrate constituted by a high-speed CMOS circuit having a high integration level at a high yield and high reliability.

公开(公告)号：US20050077550A1

公开(公告)日：2005-04-14

申请号：US10799780

申请日：2004-03-15

申请人： Satoshi Inaba ,  Makoto Fujiwara

发明人： Satoshi Inaba ,  Makoto Fujiwara

IPC分类号： H01L29/423 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/07 ,  H01L27/08 ,  H01L27/092 ,  H01L27/11 ,  H01L27/12 ,  H01L27/148 ,  H01L29/41 ,  H01L29/49 ,  H01L29/786

CPC分类号： H01L27/0924 ,  H01L21/28132 ,  H01L27/0207 ,  H01L27/0705 ,  H01L27/092 ,  H01L27/11 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

摘要： An aspect of the present invention provides a semiconductor device that includes a first transistor including a source region, a drain region provided in the same device region as the source region, and a loop-shaped gate electrode region, and a second transistor sharing, with the first transistor, the loop-shaped gate electrode region and the source region or the drain region.

摘要翻译： 本发明的一个方面提供了一种半导体器件，其包括：第一晶体管，包括源极区域，设置在与源极区域相同的器件区域中的漏极区域和环形栅电极区域;以及第二晶体管， 第一晶体管，环形栅极区域和源极区域或漏极区域。

公开(公告)号：US06844247B2

公开(公告)日：2005-01-18

申请号：US10368573

申请日：2003-02-20

申请人： Satoshi Inaba

发明人： Satoshi Inaba

IPC分类号： H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/10 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78 ,  H01L21/20 ,  H01L21/36

CPC分类号： H01L27/10894 ,  H01L21/26586 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/10873 ,  H01L29/66492

摘要： A semiconductor device Having: a semiconductor substrate; a first gate electrode constructed of a multi-layered stack member provided in a memory region, formed with memory cells, so that the first gate electrode is insulated by a first insulating layer from the semiconductor substrate; and a second gate electrode provided in a logic region, formed with a logic circuit for controlling at least the memory cells, so that the second gate electrode is insulated by a second insulating layer from a semiconductor substrate, wherein said layer, brought into contact with the first insulating layer, of the first gate electrode and the layer, brought into contact with the second insulating layer, of the second gate electrode, are composed of materials different from each other, and a method for making the same.

摘要翻译： 半导体器件具有：半导体衬底; 由设置在存储单元的存储区域中的多层叠层构件构成的第一栅电极，使得第一栅电极与第一绝缘层与半导体衬底绝缘; 以及设置在逻辑区域中的第二栅电极，形成有用于至少控制存储单元的逻辑电路，使得第二栅电极通过第二绝缘层与半导体衬底绝缘，其中所述层与 与第二栅电极的第二绝缘层接触的第一栅电极和层的第一绝缘层由彼此不同的材料构成，以及制造该第二绝缘层的方法。