公开(公告)号：US5521877A

公开(公告)日：1996-05-28

申请号：US288248

申请日：1994-08-09

申请人： Yoshiharu Aimoto

发明人： Yoshiharu Aimoto

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C8/00

CPC分类号： G11C7/103 ,  G11C7/1075

摘要： In a semiconductor memory device comprising a plurality of memory cells which are arranged on a cell area defined by a first number of column signal lines and a second number of row signal lines, a row decoder produces a row selection signal through one of the second number of row signal lines. A serial access section includes a data register and serially accesses a part of the plurality of memory cells arranged along the one end of the second number of row signal lines. The plurality of memory cells are divided into a plurality of cell blocks. The data register is divided into a plurality of subword data registers each of which corresponds to each of the plurality of cell blocks. The serial access section accesses the plurality of cell blocks, in order, at a predetermined interval. Each of the plurality of subword data registers stores subword data in each of the plurality of cell blocks, in order, at the predetermined interval.

摘要翻译： 在包括布置在由第一数量的列信号线和第二数量的行信号线限定的单元区域上的多个存储单元的半导体存储器件中，行解码器通过第二数目之一产生行选择信号 的行信号线。 串行访问部分包括数据寄存器，并且串行地访问沿着第二行行信号线的一端布置的多个存储单元的一部分。 多个存储单元被分成多个单元块。 数据寄存器被分成多个子字数据寄存器，每个子字数据寄存器对应于多个单元块中的每一个。 串行访问部分以预定间隔按顺序访问多个单元块。 多个子字数据寄存器中的每一个以预定间隔按顺序存储多个单元块中的每一个中的子字数据。

公开(公告)号：US5321665A

公开(公告)日：1994-06-14

申请号：US905690

申请日：1992-06-29

申请人： Anthony M. Balistreri ,  Andre J. Guillemaud

发明人： Anthony M. Balistreri ,  Andre J. Guillemaud

IPC分类号： H04N5/907 ,  G11C7/10 ,  G11C13/00

CPC分类号： G11C7/103 ,  G11C7/1048 ,  G11C7/1075

摘要： A data processing system includes a video random access memory with a serial register having a serial register tap addressing arrangement wherein tap addresses are decoded from column address factors and are applied to data gates associated stages of the serial register accessing data from the serial register stages. A decoder responds to a code word and generates a stages select signal that controls the data gates between the serial register stages and data lines. A plurality of code word gates, interposed in the decoder inputs and responsive to a control pulse, enable the stages select signal only while the control pulse is active. By thus limiting the decoder input to pulsed code words, sequential bit interference and inadvertent bit overwriting are avoided. An equalizer circuit, connected with each data line, equalizes the potential on the data lines before the accessed data bit is applied to the selected data line.

摘要翻译： 数据处理系统包括具有串行寄存器的视频随机存取存储器，该串行寄存器具有串行寄存器抽头寻址装置，其中抽头地址从列地址因子解码，并被应用于从串行寄存器级访问数据的串行寄存器的数据门相关级。 解码器响应码字并产生控制串行寄存器级和数据线之间的数据门的级选择信号。 插入在解码器输入端并响应于控制脉冲的多个码字门仅在控制脉冲有效时使能级选择信号。 通过这样将解码器输入限制为脉冲码字，避免了顺序位干扰和无意的位重写。 与每个数据线连接的均衡器电路在将访问的数据位应用于所选数据线之前均衡数据线上的电位。

公开(公告)号：US5299157A

公开(公告)日：1994-03-29

申请号：US727114

申请日：1991-07-09

申请人： Katsutaka Kimura ,  Takeshi Sakata ,  Kiyoo Itoh

发明人： Katsutaka Kimura ,  Takeshi Sakata ,  Kiyoo Itoh

IPC分类号： G11C11/401 ,  G11C7/06 ,  G11C7/10 ,  G11C11/419 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/02

CPC分类号： G11C7/103 ,  G11C7/06

摘要： Signals are simultaneously read out from a plurality of memory cells connected to one selected word line onto respective data lines. By successively making a selection out of data lines, signals read simultaneously onto respective data lines are serially and successively sensed by means of one signal sensing means. As for restoring operation as well, restoring is successively performed via the signal transferring means on the basis of the result sensed by the signal sensing means. By thus making a plurality of data lines share either signal sensing means or both signal sensing means and restoring means, the number of these means can be reduced and the layout pitch of these means can be relaxed. Therefore, a semiconductor memory having a higher density can be realized.

摘要翻译： 信号从连接到一个选定字线的多个存储单元同时读出到相应的数据线上。 通过连续地从数据线中进行选择，通过一个信号感测装置串行和连续地感测到同时读取到各个数据线上的信号。 对于恢复操作，也可以基于由信号感测装置感测到的结果经由信号传送装置进行恢复。 通过这样使得多个数据线共享信号感测装置或信号感测装置和恢复装置两者，可以减少这些装置的数量，并且可以放宽这些装置的布局间距。 因此，可以实现具有较高密度的半导体存储器。

公开(公告)号：US5237532A

公开(公告)日：1993-08-17

申请号：US794668

申请日：1991-11-18

申请人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Ohshima

发明人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Ohshima

IPC分类号： G11C7/10

CPC分类号： G11C7/103

摘要： In a semiconductor memory having a column-direction serial access function, two systems of circuits for selecting and fetching data are provided. A circuit operation is alternately performed such that one system is set up while the other system is accessed, thereby reducing a cycle time for a data selecting/fetching operation.

摘要翻译： 在具有列方向串行访问功能的半导体存储器中，提供用于选择和取出数据的两个电路系统。 交替执行电路操作，使得在另一个系统被访问时建立一个系统，从而减少数据选择/取出操作的周期时间。

公开(公告)号：US4992979A

公开(公告)日：1991-02-12

申请号：US231813

申请日：1988-08-12

申请人： Frederick J. Aichelman, Jr. ,  Vincent F. Sollitto, Jr.

发明人： Frederick J. Aichelman, Jr. ,  Vincent F. Sollitto, Jr.

IPC分类号： G06F11/10 ,  G06F12/04 ,  G11C7/10

CPC分类号： G06F11/1048 ,  G06F12/04 ,  G11C7/1006 ,  G11C7/103

摘要： A memory system for the transfer of a block of data, wherein the transfer of data can begin at a starting address anywhere within the block. The block is stored on two memory chips, each having multiple parallel outputs. The two chips are addressed by a common high order address bus and different low order address bus. The low order addresses are generated such that an ordered sequence of bits, beginning at the starting address, is transferred in parallel to the register from both chips, regardless of the starting address.

摘要翻译： 一种用于传送数据块的存储器系统，其中数据传输可以从块内任何地方的起始地址开始。 该块存储在两个存储器芯片上，每个存储器芯片具有多个并行输出。 这两个芯片由公共高阶地址总线和不同的低阶地址总线来寻址。 生成低阶地址，使得从起始地址开始的有序序列序列从两个码片并行传送到寄存器，而不管起始地址如何。

公开(公告)号：US3906461A

公开(公告)日：1975-09-16

申请号：US45609174

申请日：1974-03-29

申请人： SPERRY RAND CORP

发明人： CAPPON ARTHUR M

IPC分类号： G11C7/10 ,  G11C8/04 ,  G11C11/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C11/40

CPC分类号： G11C16/08 ,  G11C7/103 ,  G11C8/04 ,  G11C16/0466 ,  G11C16/10

摘要： A digital memory system employing a rectangular array of known MNOS variable threshold insulated gate field effect transistor memory cells is actuated by auxiliary cirucits which provide a four-phase operating sequence. The memory cells are arranged in word rows in which the gate electrodes of all memory cells in a given row are connected together and in bit columns having common source and common drain connections. Individual memory cells are selected by means of word-line and bit-column decoders. Each decoder includes a NOR gate matrix for selecting a given word row or bit column and a dual transistor network which superposes static and dynamic voltages on the output line of the decoder so as to increase speed and stability. The wordline decoder operates through a buffer circuit which performs code inversion and clamps all non-addressed word lines to substrate potential during switching transients. During the four-phase operating sequence, information in each memory cell in an addressed word line is read into a bit storage register wherein individual flip-flops are switched in accordance with the value of the particular bit of information. While information is temporarily stored in the bit register, each addressed memory cell is preset to a large negative threshold level and then cleared so as to be capable of retreiving information from the bit storage register during the fourth phase of the operating sequence. An input/output circuit provides means for updating the information in the bit storage register during the time that the information is temporarily stored therein or of supplying the temporarily stored information to external circuitry.

摘要翻译： 采用已知MNOS可变阈值绝缘栅场效应晶体管存储单元的矩形阵列的数字存储器系统由提供四相工作序列的辅助电路驱动。 存储单元布置成字行，其中给定行中的所有存储单元的栅极电极连接在一起，并且具有共同源极和公共漏极连接的位列。 通过字线和位列解码器选择单个存储单元。 每个解码器包括用于选择给定字行或位列的NOR门矩阵和在解码器的输出线上叠加静态和动态电压的双晶体管网络，以便提高速度和稳定性。 字线解码器通过执行代码转换的缓冲电路进行操作，并且在开关瞬变期间将所有非寻址字线钳位到衬底电位。 在四相操作序列期间，将寻址字线中的每个存储单元中的信息读入位存储寄存器，其中根据信息的特定位的值来切换各个触发器。 虽然信息被临时存储在位寄存器中，但是每个寻址的存储器单元被预置为大的负阈值电平，然后被清除，以便能够在操作序列的第四阶段期间从位存储寄存器检索信息。 输入/输出电路提供用于在信息被临时存储在其中的时间内更新位存储寄存器中的信息或者将临时存储的信息提供给外部电路的装置。

公开(公告)号：US20180204606A1

公开(公告)日：2018-07-19

申请号：US15869721

申请日：2018-01-12

申请人： Winbond Electronics Corp.

发明人： Hidemitsu KOJIMA

IPC分类号： G11C7/12 ,  G11C16/32 ,  G11C7/06 ,  G11C7/10

CPC分类号： G11C7/12 ,  G11C7/06 ,  G11C7/1021 ,  G11C7/103 ,  G11C7/109 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/32 ,  G11C2216/14

摘要： A semiconductor memory device is provided. The semiconductor memory device includes a column selection circuit, a sensing circuit, an output circuit, and a verification circuit. The column selection circuit selects n-bit data from data read from a memory cell array according to a column selection signal and outputs the selected n-bit data to an n-bit data bus. The sensing circuit senses the n-bit data on the data bus in response to an activation signal. The output circuit selects m-bit data from the n-bit data sensed by the sensing circuit in response to an internal clock signal synchronized with a serial clock signal applied from outside and outputs the selected m-bit data from output terminals. The verification circuit compares the data sensed by the sensing circuit with the data output by the output circuit to verifying the correctness of read-out data.

公开(公告)号：US20180151221A1

公开(公告)日：2018-05-31

申请号：US15840803

申请日：2017-12-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Cheng Chen ,  Jack Liu

IPC分类号： G11C11/419 ,  G11C11/418 ,  G11C13/04

CPC分类号： G11C11/419 ,  G11C7/103 ,  G11C11/418 ,  G11C13/048

摘要： A circuit includes a serializer configured to receive a non-serialized input signal having a first bit-width and generate a plurality of serialized input signals each having a second bit-width. A memory array is configured to receive each of the plurality of serialized input signals. The memory array is further configured to generate a plurality of serialized output signals. A de-serializer is configured to receive the plurality of serialized output signals and generate a non-serialized output signal. The plurality of serialized output signals each have a bit-width equal to second bit-width and the non-serialized output signal has a bit-width equal to the first bit-width.

公开(公告)号：US09659610B1

公开(公告)日：2017-05-23

申请号：US15158205

申请日：2016-05-18

申请人： Micron Technology, Inc.

发明人： Glen E. Hush

IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C7/12 ,  G11C7/06 ,  G11C19/28 ,  G11C7/08

CPC分类号： G11C7/1036 ,  G11C5/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/103 ,  G11C7/1048 ,  G11C7/12 ,  G11C19/28 ,  G11C2207/005

摘要： The present disclosure includes apparatuses and methods related to shifting data. A number of embodiments include an apparatus comprising pre-charge lines and n-channel transistors without complementary p-channel transistors. A number of embodiments include a method comprising shifting data by pre-charging nodes with an operating voltage.

公开(公告)号：US20150071001A1

公开(公告)日：2015-03-12

申请号：US14204565

申请日：2014-03-11

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Naoaki KANAGAWA

IPC分类号： G11C7/10 ,  G11C16/06

CPC分类号： G11C7/10 ,  G11C7/103 ,  G11C7/1087 ,  G11C16/06

摘要： A semiconductor memory device according to an embodiment is provided with a plurality of first latch circuits that latch setting-data at different timings, a plurality of hold circuits provided corresponding to the respective plurality of first latch circuits, each holding data latched by the corresponding first latch circuit, and an address decoder that decodes an address that specifies a destination to hold data. Each of the plurality of hold circuits has one or more holding parts that hold data latched by the corresponding first latch circuit based on a decode signal decoded by the address decoder.

摘要翻译： 根据实施例的半导体存储器件设置有多个第一锁存电路，其以不同的定时锁存设置数据;对应于多个第一锁存电路设置的多个保持电路，每个保持电路保持由相应的第一 锁存电路，以及解码指定保存数据的目的地的地址的地址解码器。 多个保持电路中的每一个具有一个或多个保持部分，其基于由地址解码器解码的解码信号来保存由相应的第一锁存电路锁存的数据。