公开(公告)号：US06492966B1

公开(公告)日：2002-12-10

申请号：US08281912

申请日：1994-07-27

Applicant: Alton O. Christensen

Inventor： Alton O. Christensen

IPC: G09G330

CPC classification number: H01J1/3042 ,  H01J2201/30403 ,  H01J2201/319

Abstract: Triode pixel devices and complementary triode logic devices for control of the pixel devices are disclosed. The pixel and logic devices are integrally fabricated in arrays suitable for full color flat display panels. Both pixel and logic elements are operated in a gate controlled avalanche mode. Pixel elements are formed from organic or inorganic electroluminescent (EL) materials ohmically contacted by low work function metal. The depletion region necessary for controlling EL intensity or preventing EL avalanche is affected by potentials to a gate element injected into the EL material. The shape of the gate element multiplies the field produced by the gate potential. Luminescence is directly viewed from the brighter, lateral EL emission not available in the prior art. The complementary logic devices are formed from separate depositions of n-type and p-type silicon with their respective gates connected in common. A manufacturing process to produce economical full color, large area, flat-panel, displays of high pixel density and redundancy is described. Small area high pixel density displays suitable for head-mounted military, avionic, and virtual reality display products are also discussed.

Abstract translation: 公开了用于控制像素装置的三极体像素装置和互补三极管逻辑装置。 像素和逻辑器件被整体地制成阵列，适用于全彩平板显示面板。 像素和逻辑元件都以栅极控制的雪崩模式工作。 像素元件由低功函数金属欧姆接触的有机或无机电致发光（EL）材料形成。 用于控制EL强度或防止EL雪崩所需的耗尽区受到注入到EL材料中的栅极元件的电位的影响。 栅极元件的形状将由栅极电位产生的场相乘。 从现有技术中不可获得的较亮的侧向EL发射中直接观察发光。 互补逻辑器件由n型和p型硅的分开沉积形成，其相应的栅极共同连接。 描述了生产经济的全彩色，大面积，平板，高像素密度和冗余的显示器的制造工艺。 还讨论了适用于头戴式军用，航空电子和虚拟现实显示产品的小面积高像素密度显示器。

公开(公告)号：US06426234B2

公开(公告)日：2002-07-30

申请号：US09782396

申请日：2001-02-13

Applicant: Terry L. Gilton

Inventor： Terry L. Gilton

IPC: H01L2100

CPC classification number: H01J9/025 ,  H01J2201/30403 ,  H01J2209/0226

Abstract: A process is provided for forming sharp asperities useful as field emitters. The process comprises patterning and doping a silicon substrate. The doped silicon substrate is anodized. The anodized area is then use for field emission tips. The process of the present invention is also useful for low temperature sharpening of tips fabricated by other methods. The tips are anodized, and then exposed to radiant energy and the resulting oxide is removed.

Abstract translation: 提供了用于形成用作场致发射体的尖锐凹凸的工艺。 该工艺包括图案化和掺杂硅衬底。 掺杂硅衬底被阳极氧化。 然后阳极氧化区域用于场发射尖端。 本发明的方法也可用于通过其它方法制造的尖端的低温磨削。 尖端被阳极氧化，然后暴露于辐射能，并且所得到的氧化物被去除。

公开(公告)号：US20010018222A1

公开(公告)日：2001-08-30

申请号：US09782396

申请日：2001-02-13

Inventor： Terry L. Gilton

IPC: H01L021/00

CPC classification number: H01J9/025 ,  H01J2201/30403 ,  H01J2209/0226

Abstract: A process is provided for forming sharp asperities useful as field emitters. The process comprises patterning and doping a silicon substrate. The doped silicon substrate is anodized. The anodized area is then used for field emission tips. The process of the present invention is also useful for low temperature sharpening of tips fabricated by other methods. The tips are anodized, and then exposed to radiant energy and the resulting oxide is removed.

Abstract translation: 提供了用于形成用作场致发射体的尖锐凹凸的工艺。 该工艺包括图案化和掺杂硅衬底。 掺杂硅衬底被阳极氧化。 然后将阳极氧化区域用于场发射尖端。 本发明的方法也可用于通过其它方法制造的尖端的低温磨削。 尖端被阳极氧化，然后暴露于辐射能，并且所得到的氧化物被去除。

公开(公告)号：US06235545B1

公开(公告)日：2001-05-22

申请号：US09251262

申请日：1999-02-16

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01L2100

CPC classification number: H01J9/025 ,  H01J2201/30403

Abstract: In one aspect, the invention encompasses a method of treating the end portions of an array of substantially upright silicon-comprising structures. A substrate having a plurality of substantially upright silicon-comprising structures extending thereover is provided. The substantially upright silicon-comprising structures have base portions, and have end portions above the base portions. A masking layer is formed over the substrate to cover the base portions of the substantially upright silicon-comprising structures while leaving the end portions exposed. The end portions are then exposed to conditions which alter the end portions relative to the base portions. In another aspect, the invention encompasses a method of treating the ends of an array of silicon-comprising emitter structures. A substrate having a plurality of silicon-comprising emitter structures thereover is provided. The emitter structures have base portions and ends above the base portions. A layer of spin-on-glass is formed over the substrate. The layer of spin-on-glass covers the base portions of the emitter structures and leaves the ends exposed. The ends are then exposed to conditions which alter the ends relative to the base portions. In yet another aspect, the invention encompasses a cathode assembly which includes a plurality of silicon-comprising emitter structures projecting over a substrate. The emitter structures have base portions and ends above the base portions, and the ends comprise a different material than the base portions.

Abstract translation: 在一个方面，本发明包括一种处理基本上直立的含硅结构阵列的端部的方法。 提供了一种具有多个基本上直立的含硅结构延伸到其上的衬底。 基本上直立的含硅结构具有基部，并且在基部上方具有端部。 掩模层形成在衬底上以覆盖基本上直立的含硅结构的基部，同时使端部露出。 然后将端部暴露于相对于基部改变端部的条件。 在另一方面，本发明包括处理含硅发射体结构阵列的端部的方法。 提供了具有多个其上含硅的发射体结构的衬底。 发射极结构具有基部并且在基部上方结束。 在衬底上形成一层旋涂玻璃。 旋涂玻璃层覆盖发射器结构的基部并使端部露出。 然后将端部暴露于相对于基部改变端部的条件。 在另一方面，本发明包括阴极组件，其包括在衬底上突出的多个包含硅的发射器结构。 发射极结构具有基部和端部在基部之上，并且端部包括与基部不同的材料。

公开(公告)号：US06169528A

公开(公告)日：2001-01-02

申请号：US08689656

申请日：1996-08-13

Applicant: Takahiro Oguchi ,  Hidetoshi Suzuki ,  Kunihiro Sakai ,  Takamasa Sakuragi ,  Yasuyuki Todokoro

Inventor： Takahiro Oguchi ,  Hidetoshi Suzuki ,  Kunihiro Sakai ,  Takamasa Sakuragi ,  Yasuyuki Todokoro

IPC: G09G322

CPC classification number: G09G3/2011 ,  B82Y10/00 ,  G09G3/2014 ,  G09G3/22 ,  G09G2310/027 ,  G09G2310/0272 ,  G09G2310/0275 ,  G09G2320/0223 ,  H01J2201/30403 ,  H01J2201/3165 ,  H01J2329/00

Abstract: In order to prevent voltage drops across the wiring resistances in a multi-electron source having a plurality of electron emitters wired in the form of a matrix through a plurality of data wiring layers and a plurality of scanning wiring layers, a constant current signal is output to each data wiring layer. At this time, each non-selected data wiring layer tends to be set at a high impedance and vary in potential, resulting in an abnormal turn-on operation or an electron orbit shift. A driving circuit for solving this problem is provided. A switch for switching a constant current output unit for outputting a constant current regardless of the impedance of a signal output destination, and a constant voltage output unit for outputting a constant voltage regardless of the impedance of a signal output destination is connected to each data wiring layer. For example, a constant-current circuit (17) as a current output unit always outputs the same current (I1 to In) to a switch (30). A pulse width signal (PW1 to PWn) from a pulse-width modulation circuit (7) serves to switch the mode of outputting a current (I1 to In) to a data wiring layer (Dy1 to Dyn) and the mode of fixing a data wiring layer to voltage GND.

Abstract translation: 为了防止具有通过多个数据布线层和多​​个扫描布线层以矩阵形式布线的多个电子发射体的多电子源中的布线电阻之间的电压降，输出恒定电流信号 到每个数据布线层。 此时，每个未选择的数据布线层倾向于设置为高阻抗并且电位变化，导致异常接通操作或电子轨道偏移。 提供了解决这个问题的驱动电路。 用于切换用于输出恒定电流的恒定电流输出单元的开关，而不管信号输出目的地的阻抗如何，以及用于输出恒定电压而不管信号输出目的地的阻抗的恒定电压输出单元连接到每个数据布线 层。 例如，作为电流输出单元的恒流电路（17）总是向开关（30）输出相同的电流（I1〜In）。 来自脉冲宽度调制电路（7）的脉冲宽度信号（PW1〜PWn）用于将输出电流（I1〜In）的模式切换为数据布线层（Dy1〜Dyn）和固定数据的方式 接线层到电压GND。

公开(公告)号：US6165374A

公开(公告)日：2000-12-26

申请号：US354529

申请日：1999-07-15

Applicant: David A. Cathey ,  Kevin Tjaden

Inventor： David A. Cathey ,  Kevin Tjaden

IPC: H01J9/02 ,  B44C1/22 ,  H01L21/00

CPC classification number: H01J9/025 ,  H01J2201/30403

Abstract: A method for fabricating sharp asperities. A substrate is provided which has a mask layer disposed thereon, and a layer of micro-spheres is disposed superjacent the mask layer. The micro-spheres are for patterning the mask layer. Portions of the mask layer are selectively removed, thereby forming circular masks. The substrate is isotropically etched, thereby creating sharp asperities.

Abstract translation: 一种制造尖锐凹凸的方法。 提供了具有设置在其上的掩模层的基板，并且在该掩模层的上方布置一层微球。 微球用于图案化掩模层。 选择性地去除掩模层的一部分，从而形成圆形掩模。 基板被各向同性地蚀刻，从而产生尖锐的凹凸。

公开(公告)号：US6100627A

公开(公告)日：2000-08-08

申请号：US869465

申请日：1997-06-05

Applicant: Corrado Carretti ,  Bruno Ferrario

Inventor： Corrado Carretti ,  Bruno Ferrario

IPC: C22C14/00 ,  C22C16/00 ,  H01J7/14 ,  H01J7/18 ,  H01J9/26 ,  H01J9/38 ,  H01J9/39 ,  H01J17/24 ,  H01J29/94 ,  H01J31/12 ,  H01J1/02 ,  H01J1/62 ,  H01J17/22 ,  H01J63/04

CPC classification number: H01J7/183 ,  H01J29/94 ,  H01J7/18 ,  H01J2201/30403 ,  H01J2329/00

Abstract: A Field Emitter Device (FED) having a substantially reducing atmosphere is described. The atmosphere in a FED can be maintained substantially free of oxidizing gases and includes a partial pressure of hydrogen between about 1.times.10.sup.-7 millibar (mbar) and 1.times.10.sup.-3 mbar. In one embodiment, a non-evaporable getter material previously charged with hydrogen gas is placed inside the FED before the FED is sealed. The non-evaporable getter material can be charged by exposure to hydrogen gas at a pressure between about 1.times.10.sup.-4 and about 2 bar. Subsequently, the components forming the FED are sealed, and the FED is evacuated and hermetically sealed to the outside atmosphere.

Abstract translation: 描述了具有显着降低的气氛的场发射器装置（FED）。 FED中的气氛可以基本上不含氧化气体，并且包括在约1×10-7毫巴（mbar）至1×10-3毫巴之间的氢气分压。 在一个实施例中，在FED密封之前，预先装入氢气的非蒸发性吸气剂材料放置在FED的内部。 可以在约1×10 -4至约2巴之间的压力下暴露于氢气来对非蒸发性吸气材料进行充电。 随后，将形成FED的部件密封，将FED抽真空并密封到外部气氛。

公开(公告)号：US6042443A

公开(公告)日：2000-03-28

申请号：US321509

申请日：1999-05-27

Applicant: Sergio Carella ,  Claudio Boffito

Inventor： Sergio Carella ,  Claudio Boffito

IPC: H01J7/18 ,  H01J9/39 ,  H01J29/94 ,  H01J31/12 ,  H01J9/385

CPC classification number: H01J9/39 ,  H01J29/94 ,  H01J7/183 ,  H01J2201/30403 ,  H01J2209/385 ,  H01J2329/00

Abstract: A process for producing a field emitter flat display includes providing a supported porous layer of a non-evaporable getter material by depositing the non-evaporable getter material on a substrate followed by sintering the deposited material. The substrate having the porous layer of non-evaporable getter material thereon is then housed in an inner space defined by opposing plates. The inner space is then evacuated and hermetically sealed. The non-evaporable getter material is preferably deposited by preparing a suspension of non-evaporable getter material particles in a suspending medium, coating a surface of a substrate with the suspension by, e.g., spraying, and sintering the coating.

Abstract translation: 制造场致发射体平面显示器的方法包括通过将不可蒸发的吸气剂材料沉积在基底上，然后烧结沉积的材料来提供不可蒸发的吸气剂材料的支撑多孔层。 然后将具有其上的不可蒸发的吸气剂材料的多孔层的基底容纳在由相对的板限定的内部空间中。 然后将内部空间抽真空并密封。 非蒸发性吸气剂材料优选通过将悬浮介质中的非蒸发性吸气材料颗粒的悬浮液制备而沉积，通过例如喷涂和烧结涂层将悬浮液的表面涂覆在基材表面上。

公开(公告)号：US6028575A

公开(公告)日：2000-02-22

申请号：US689658

申请日：1996-08-13

Applicant: Yasuyuki Todokoro ,  Hidetoshi Suzuki

Inventor： Yasuyuki Todokoro ,  Hidetoshi Suzuki

IPC: G09G3/20 ,  G09G3/22 ,  H01J1/316

CPC classification number: G09G3/2011 ,  B82Y10/00 ,  G09G3/2014 ,  G09G3/22 ,  G09G2310/027 ,  G09G2310/0275 ,  G09G2320/0223 ,  H01J2201/30403 ,  H01J2201/3165 ,  H01J2329/00

Abstract: In order to cause a multi-electron source having electron emitters wired in the form of a matrix to emit electrons without any variations, there is provided an electron generating device including a multi-electron source (601) having a plurality of electron emitters (1002) wired in the form of a matrix through a plurality of data wiring layers (1004) and a plurality of scanning wiring layers (1003), and a driving circuit for driving the multi-electron source (601), the driving circuit including a first driving means (603) for applying a first voltage (Vs) to a scanning wiring layer to which an electron emitter which is to emit electrons is connected, and applying a second voltage (Vns) to a scanning wiring layer to which an electron emitter which is not to emit electrons is connected, and a second driving means (602) for applying a third voltage (Ve) to a data wiring layer to which an electron emitter which is to emit electrons is connected, and applying a fourth voltage (Vg) to a data wiring layer to which an electron emitter which is not to emit electrons is connected, wherein the second voltage (Vns) is substantially equal to the third voltage (Ve).

公开(公告)号：US6019657A

公开(公告)日：2000-02-01

申请号：US183601

申请日：1998-10-29

Applicant: Kishore K. Chakvorty ,  Swayambu Ramani

Inventor： Kishore K. Chakvorty ,  Swayambu Ramani

IPC: H01J1/30 ,  H01J3/02 ,  H01J9/02 ,  H01J9/14 ,  H01J29/04 ,  H01J31/12

CPC classification number: H01J3/022 ,  H01J1/30 ,  H01J9/025 ,  H01J9/14 ,  H01J2201/30403 ,  H01J2329/00

Abstract: A flat panel display and a method for forming a flat panel display. In one embodiment, the flat panel display includes a cathodic structure which is formed within an active area on a backplate. The cathodic structure includes a row metal composed of strips of aluminum overlain by a layer of cladding material. The use of aluminum and cladding material to form row metal gives row metal segments which are highly conductive due to the high conductivity of aluminum. By using a suitable cladding material and processing steps, a bond between the aluminum and the cladding material is formed which has good electrical conductivity. In one embodiment, tantalum is used as a cladding material. Tantalum forms a bond with the overlying resistive layer which has good electrical conductivity. Thus, the resulting structure has very high electrical conductivity through the aluminum layer and high conductivity into the resistive layer.

Abstract translation: 平板显示器和平板显示器的形成方法。 在一个实施例中，平板显示器包括形成在背板上的有效区域内的阴极结构。 阴极结构包括由覆盖材料层覆盖的铝条构成的行金属。 使用铝和包层材料形成行金属，由于铝的高导电性而导致高导电性的行金属片段。 通过使用合适的覆层材料和加工步骤，形成铝和包层材料之间的结合，其具有良好的导电性。 在一个实施例中，钽用作包层材料。 钽与具有良好导电性的上覆电阻层形成键。 因此，所得到的结构通过铝层具有非常高的导电性，并且在电阻层中具有高导电性。