公开(公告)号：US5867524A

公开(公告)日：1999-02-02

申请号：US800890

申请日：1997-02-13

Applicant: James Ronald Booth ,  Donald Reid Bush ,  John Thomas Fessler ,  Keith Bryan Hardin

Inventor： James Ronald Booth ,  Donald Reid Bush ,  John Thomas Fessler ,  Keith Bryan Hardin

IPC: G06F15/78 ,  G06F1/04 ,  H03B29/00 ,  H03C3/09 ,  H03K4/94 ,  H03L7/197 ,  H04B15/00

CPC classification number: H03C3/0966 ,  H03B29/00 ,  H03C3/0925 ,  H03C3/0941 ,  H03L7/0805 ,  H03L7/197 ,  H04B2215/064 ,  H04B2215/067

Abstract: A clock circuit includes an oscillator for generating a reference frequency signal, and a spread spectrum clock generator cooperating with the oscillator for generating a spread spectrum clock output signal having a fundamental frequency and reduced amplitude EMI spectral components at harmonics of the fundamental frequency. The spread spectrum clock generator preferably includes a clock pulse generator for generating a series of clock pulses, and a spread spectrum modulator for frequency modulating the clock pulse generator to broaden and flatten amplitudes of EMI spectral components which would otherwise be produced by the clock pulse generator. The spread spectrum modulator frequency modulates the clock pulses with specific profiles of frequency deviation versus the period of the profile. Electronic devices including the spread spectrum clock circuit and associated method are also disclosed.

Abstract translation: 时钟电路包括用于产生参考频率信号的振荡器和与振荡器协作的扩展频谱时钟发生器，用于产生具有在基频的谐波处的基频和降低幅度的EMI频谱分量的扩频时钟输出信号。 扩频时钟发生器优选地包括用于产生一系列时钟脉冲的时钟脉冲发生器和用于对时钟脉冲发生器进行频率调制的扩展频谱调制器，以扩大和平缓由EMI时钟脉冲发生器产生的EMI频谱分量的幅度 。 扩频调制器利用频率偏差的特性曲线与轮廓周期调制时钟脉冲。 还公开了包括扩频时钟电路和相关方法的电子设备。

公开(公告)号：US5834987A

公开(公告)日：1998-11-10

申请号：US902836

申请日：1997-07-30

Applicant: Paul Wilkinson Dent

Inventor： Paul Wilkinson Dent

IPC: H03C3/09 ,  H03L7/197 ,  H03C3/00 ,  H03C1/00 ,  H03K7/02 ,  H03L7/18

CPC classification number: H03C3/0975 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0966 ,  H03L7/1974 ,  H03L7/1976

Abstract: A frequency synthesizer includes a controlled oscillator which is responsive to a frequency control input signal, to generate an output frequency. A programmable frequency divider is responsive to the output frequency and to a divider control input, to divide the output frequency by a first integral ratio or by a second integral ratio in response to the divider control input, to thereby produce a divided signal. A phase comparator is responsive to a reference frequency signal and to the divided signal, to compare the reference frequency signal and the divided signal, and thereby produce a first error signal. A sigma-delta modulator is responsive to a modulation input to produce the divider control input. A loop filter is responsive to the first error signal, to thereby produce the frequency control input signal. Ripple compensation signals and direct modulation signals may also be provided, to provide a three-point modulator for a frequency synthesizer. Analog and digital embodiments may also be provided.

Abstract translation: 频率合成器包括响应于频率控制输入信号的受控振荡器，以产生输出频率。 可编程分频器响应于输出频率和分频器控制输入，以响应于分频器控制输入将输出频率除以第一积分比或第二积分比，从而产生分频信号。 相位比较器响应于参考频率信号和分频信号，以比较参考频率信号和分频信号，从而产生第一误差信号。 Σ-Δ调制器响应于调制输入以产生除法器控制输入。 环路滤波器响应于第一误差信号，从而产生频率控制输入信号。 还可以提供纹波补偿信号和直接调制信号，以提供用于频率合成器的三点调制器。 还可以提供模拟和数字实施例。

公开(公告)号：US5483203A

公开(公告)日：1996-01-09

申请号：US332973

申请日：1994-11-01

Applicant: Alan P. Rottinghaus

Inventor： Alan P. Rottinghaus

IPC: H03C3/09 ,  H03L7/189

CPC classification number: H03C3/095 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03L7/189

Abstract: A frequency synthesizer 10 having a digital to analog converter (DAC) 40 and a feedback system which detects the deviation of a frequency modulated signal and aligns the detected deviation. DAC 40 provides a presteering stimulus for alignment purposes. After presteering alignment, the gain of DAC 40 is accurately set for frequency deviation because modulation is sourced from the same digital to analog converter that performs presteering.

Abstract translation: 具有数模转换器（DAC）40的频率合成器10和检测频率调制信号的偏差并对准所检测的偏差的反馈系统。 DAC 40提供了用于对准目的的预引导刺激。 在预引导对准之后，DAC 40的增益被精确地设置为频率偏差，因为调制源自执行预转向的相同的数模转换器。

公开(公告)号：US4942374A

公开(公告)日：1990-07-17

申请号：US343484

申请日：1989-04-25

Applicant: Kenji Sai

Inventor： Kenji Sai

IPC: H03C3/00 ,  H03C3/09

CPC classification number: H03C3/0975 ,  H03C3/0941 ,  H03C3/095 ,  H03C2200/005 ,  H03C2200/0054

Abstract: In a phase-locked loop type synthesizer comprising a phase-locked loop which comprises a phase comparator, a loop filter, a voltage controlled oscillator having a gain Kv, and a circuit for feeding back an output from the voltage controlled oscillator to the phase comparator through a frequency divider having a frequency division ratio N and which is supplied with first and second modulation signals at first and second sections through first and second adders, first and second gain control circuits are provided on input lines of the first and the second modulation signals, respectively. The first gain control circuit has a first gain adjusted to be in inverse proportion to the frequency division ratio N while the second gain control circuit has a second gain adjusted to be in inverse proportion to the gain Kv. Preferably, the first adder is connected between the phase comparator and the loop filter while the second adder is connected between the loop filter and the voltage controlled oscillator. If the voltage controlled oscillator is of the fixed gain type, the second gain control circuit may be omitted.

公开(公告)号：US4890071A

公开(公告)日：1989-12-26

申请号：US262767

申请日：1988-10-26

Applicant: George S. Curtis

Inventor： George S. Curtis

IPC: H03L7/187 ,  H03B1/00 ,  H03C3/00 ,  H03C3/09 ,  H03C3/22 ,  H03L7/081 ,  H03L7/113 ,  H03L7/18 ,  H03L7/189 ,  H03L7/197

CPC classification number: H03C3/0975 ,  H03C3/0925 ,  H03C3/0941 ,  H03L7/081 ,  H03L7/113 ,  H03L7/189 ,  H03L7/197 ,  H03B2201/0208 ,  H03C2200/005 ,  H03C2200/0083 ,  H03C3/22

Abstract: A programmable low noise frequency modulated signal source including a voltage controlled oscillator (VCO) having a frequency locked loop (FLL) constituting a first feedback path and a phase lock loop (PLL) constituting a second feedback path is provided. The PLL includes a VCO, a programmable fractional-N frequency division network and a phase detector for comparing the phase of the VCO output signal with the phase of a reference signal and for producing an error signal to controllably adjust the output frequency of the VCO. The FLL includes a delay line frequency discriminator, a loop amplifier and filter to provide a feedback signal to a frequency control terminal of the VCO. The frequency discriminator includes a first signal path having a frequency sensitive time delay network to provide a phase shift as a function of the VCO output signal frequency and a second signal path which includes a voltage controlled phase shifting network. The error signal derived from the PLL phase detector is coupled to an input terminal at the voltage controlled phase shifting network. The PLL error signal in combination with a bias signal adjusts the phase difference between the two frequency discriminator signal paths to set the operating point of the FLL phase detector such that the VCO output signal will have a desired frequency and minimum phase noise.

公开(公告)号：US4562414A

公开(公告)日：1985-12-31

申请号：US565947

申请日：1983-12-27

Applicant: Donald L. Linder ,  William R. Murphy

Inventor： Donald L. Linder ,  William R. Murphy

IPC: H03C3/09 ,  H03C3/00

CPC classification number: H03C3/0983 ,  H03C3/0933 ,  H03C3/0941

Abstract: There is disclosed a new and improved frequency modulation system and method for providing a frequency modulated signal which varies in frequency from a center frequency in response to the amplitude of an analog modulating signal. The system and method utilizes a frequency shift synthesizer to provide the frequency modulated signal and digital techniques for quantizing the amplitude modulating signal and providing dividing factors to the frequency shift synthesizer responsive to the amplitude quantization.

Abstract translation: 公开了一种新的改进的频率调制系统和方法，用于响应于模拟调制信号的振幅，提供频率随中心频率变化的频率调制信号。 该系统和方法利用频移合成器提供频率调制信号和用于量化幅度调制信号的数字技术，并且响应于幅度量化向频移合成器提供分频因子。

公开(公告)号：US4546331A

公开(公告)日：1985-10-08

申请号：US581767

申请日：1984-02-21

Applicant: Marcus K. DaSilva ,  David P. Whipple ,  Robert E. Temple

Inventor： Marcus K. DaSilva ,  David P. Whipple ,  Robert E. Temple

IPC: H03C3/00 ,  H03C3/02 ,  H03C3/09 ,  H03L7/197

CPC classification number: H03C3/0975 ,  H03C3/0941 ,  H03C3/095 ,  H03L7/197 ,  H03C3/02

Abstract: Apparatus is provided to frequency modulate (FM) RF carrier frequencies generated in a phase-locked loop (PLL). FM outside the loop bandwidth is AC coupled to the loop. FM within the loop bandwidth is DC coupled via an integrating OP-AMP to provide phase modulation. Whenever the output of the integrator exceeds a preset threshold, a prescaler removes or adds two pi (or integral multiples of two pi) radians of phase change from the input to the loop divide-by-N circuit. At the same time, a current source pumps charge into the integrator to exactly compensate for the amount of phase removed or added resetting the integrator. DC feedback around the integrating OP-AMP and a feedback signal proportional to the exact amount of phase added or removed provides a true synthesized loop center frequency with no drift. When the feedback path is interrupted, DC FM is provided.

Abstract translation: 提供了在锁相环（PLL）中产生的频率调制（FM）RF载波频率的装置。 FM外环带宽是交流耦合到环路。 环路带宽内的FM通过集成OP-AMP直流耦合，以提供相位调制。 每当积分器的输出超过预设阈值时，预分频器将从输入到环路除N电路中移除或添加两个相位变化的pi（或两个π）的整数倍。 同时，电流源将电荷泵送到积分器中，以精确地补偿去除的量或增加的积分器复位量。 集成OP-AMP周围的DC反馈和与精确相位相加成正比的反馈信号提供了一个没有漂移的真正的合成回路中心频率。 当反馈路径中断时，提供DC FM。

公开(公告)号：US4528522A

公开(公告)日：1985-07-09

申请号：US420690

申请日：1982-09-12

Applicant: Takashi Matsuura

Inventor： Takashi Matsuura

IPC: H04B1/40 ,  H03C3/08 ,  H03C3/09 ,  H04B1/04 ,  H04B1/26 ,  H04B1/50 ,  H03L7/22

CPC classification number: H03C3/095 ,  H03C3/0925 ,  H03C3/0941

Abstract: A frequency synthesizer used for a frequency modulation (FM) transceiver which uses negative feedback to make the modulation characteristics linear and stable over a wide frequency range. The negative feedback is comprised of a frequency mixer, which mixes the outputs of a local oscillator and a voltage controlled oscillator, and a frequency divider and demodulator, which act on the output of the frequency mixer and supply the demodulated output signal to an adder, where it is added in reverse phase to the modulating signal.

Abstract translation: 用于频率调制（FM）收发器的频率合成器，其使用负反馈使调制特性在宽的频率范围内线性和稳定。 负反馈包括混频本地振荡器和压控振荡器的输出的混频器和分频器和解调器，分频器和解调器作用于混频器的输出端并将解调的输出信号提供给加法器， 其中与调制信号反向相加。

公开(公告)号：US4477919A

公开(公告)日：1984-10-16

申请号：US251572

申请日：1981-04-06

Applicant: Jaime A. Borras ,  Ruben J. Gonzalez

Inventor： Jaime A. Borras ,  Ruben J. Gonzalez

IPC: H03C3/09 ,  H03C3/22 ,  H03D13/00 ,  H03J5/02 ,  H03K23/66 ,  H03L7/08 ,  H03L7/193 ,  H03L7/199 ,  H04B1/40 ,  H03K21/36

CPC classification number: H03K21/38 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0966 ,  H03C3/227 ,  H03D13/005 ,  H03J5/0281 ,  H03K23/667 ,  H03L7/0802 ,  H03L7/193 ,  H03L7/199 ,  H04B1/405

Abstract: A frequency synthesized transceiver capable of tuning to a plurality of communication channels is disclosed. The transceiver includes a receiver section and a transmitter section which are coupled to the synthesizer which generates the appropriate injection signals to achieve tuning. The frequency synthesizer includes a multiposition switch which accesses various addressable memory locations in a programmable read-only memory where the appropriate divisors are stored to cause tuning of the synthesizer to the appropriate communication channel. A zone selector switch enables grouping and easy retrievability of channels. The divisors are supplied to a single synchronous binary swallow counter which works in conjunction with a dual modulus prescaler to monitor the frequency output of the voltage controlled oscillator. A programmable divider coupled to a reference oscillator source is compared with the output of the synchronous counter in a digital and analog phase detector. The phase detector supplies signals through a loop filter to apply the appropriate voltage to the voltage controlled oscillator. The phase detector includes means to rapid advance the voltage controlled oscillator to cause frequency tuning.

Abstract translation: 公开了能够调谐到多个通信信道的频率合成收发器。 收发器包括接收器部分和发射器部分，其耦合到合成器，其产生适当的注入信号以实现调谐。 频率合成器包括一个多位开关，该多位开关访问可编程只读存储器中的各种可寻址存储器位置，其中存储适当的除数以使合成器调谐到合适的通信信道。 区域选择开关使分组和通道容易检索。 除数被提供给单个同步二进制吞咽计数器，其与双模预分频器一起工作以监视压控振荡器的频率输出。 耦合到参考振荡器源的可编程分频器与数字和模拟相位检测器中的同步计数器的输出进行比较。 相位检测器通过环路滤波器提供信号，以将适当的电压施加到压控振荡器。 相位检测器包括用于快速推进压控振荡器以引起频率调谐的装置。

公开(公告)号：US4472820A

公开(公告)日：1984-09-18

申请号：US251658

申请日：1981-04-06

Applicant: Jaime A. Borras

Inventor： Jaime A. Borras

IPC: H03C3/09 ,  H03C3/22 ,  H03D13/00 ,  H03J5/02 ,  H03K23/66 ,  H03L7/08 ,  H03L7/193 ,  H03L7/199 ,  H04B1/40 ,  H03K21/36

CPC classification number: H03K21/38 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0966 ,  H03C3/227 ,  H03D13/005 ,  H03J5/0281 ,  H03K23/54 ,  H03K23/667 ,  H03L7/0802 ,  H03L7/193 ,  H03L7/199 ,  H04B1/405

Abstract: In a transceiver, a synthesizer includes a multiposition switch which accesses various addressable memory locations in a programmable read-only memory (PROM), where the appropriate divisors are stored to cause tuning of the synthesizer to the appropriate communication channel. A zone selector switch enables grouping and easy retrievability of channels. The divisors are supplied to a single synchronous binary swallow counter which works in conjunction with a dual modulus prescaler to monitor the frequency output of the voltage controlled oscillator. In the swallow counting device, two latches receive divisor related information supplied by the PROM. When the sampled state of a single up counter reaches a first latched number, the prescaler changes the modulus. Synchronous counting then continues, without reprogramming new values. When the up counter reaches a second latched number, a predetermined frequency ratio has been achieved, and the counter is reset.

Abstract translation: 在收发器中，合成器包括一个多位开关，该多位开关访问可编程只读存储器（PROM）中的各种可寻址存储器位置，其中存储适当的除数以使合成器调谐到合适的通信信道。 区域选择开关使分组和通道容易检索。 除数被提供给单个同步二进制吞咽计数器，其与双模预分频器一起工作以监视压控振荡器的频率输出。 在吞咽计数装置中，两个锁存器接收由PROM提供的除数相关信息。 当单个向上计数器的采样状态达到第一个锁存数时，预分频器将改变模数。 然后，同步计数继续，而不重新编程新值。 当向上计数器达到第二个锁存数时，已经达到预定的频率比，并且计数器被复位。