公开(公告)号：US09837413B2

公开(公告)日：2017-12-05

申请号：US15041593

申请日：2016-02-11

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Sotirios Athanasiou

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L21/84 ,  H01L29/786 ,  H01L21/8238 ,  H01L23/528 ,  H01L21/82 ,  H01L29/10 ,  H01L29/165 ,  H01L29/08

CPC classification number: H01L27/092 ,  H01L21/8238 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/528 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78615 ,  H01L29/78648 ,  H01L29/78654

Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.

公开(公告)号：US20170346825A1

公开(公告)日：2017-11-30

申请号：US15358854

申请日：2016-11-22

Applicant: STMicroelectronics SA

Inventor： Jocelyn Leheup

IPC: H04L29/06

CPC classification number: H04L63/10 ,  G06F21/10 ,  H04L63/0428 ,  H04L63/102 ,  H04L63/1416 ,  H04L63/1425 ,  H04L63/1441 ,  H04L63/20 ,  H04N21/4405 ,  H04N21/4623 ,  H04N21/4627

Abstract: A device protects an incoming multimedia signal with a protection that is controllable and configured for enabling or disabling an application for an interface protection on an outgoing signal coming from the incoming signal. An output interface is configured for delivering the outgoing signal on an output. An authorization process is performed for authorizing or otherwise a control over the enabling or disabling of the interface protection application depending on security rules.

公开(公告)号：US20170301681A1

公开(公告)日：2017-10-19

申请号：US15377861

申请日：2016-12-13

Applicant: STMicroelectronics SA

Inventor： Stephane Denorme ,  Philippe Candelier

IPC: H01L27/112 ,  H01L23/00 ,  H01L23/525 ,  H01L27/02 ,  G11C17/16

CPC classification number: H01L27/11206 ,  G11C11/005 ,  G11C17/10 ,  G11C17/16 ,  H01L23/5252 ,  H01L23/57 ,  H01L27/0203

Abstract: A configurable read only memory (ROM) including a number of memory cells. The memory cells include first-type memory cells that are electrically-programmable antifuses and second-type memory cells that are antifuses programmed by masking.

公开(公告)号：US20170301072A1

公开(公告)日：2017-10-19

申请号：US15636294

申请日：2017-06-28

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics SA

Inventor： Mahesh CHANDRA ,  Antoine DROUOT

IPC: G06T5/20 ,  G06T11/60 ,  G06T5/00

CPC classification number: G06T5/20 ,  G06K9/4604 ,  G06K9/4671 ,  G06K9/56 ,  G06T5/002 ,  G06T11/60 ,  G06T2207/10016

Abstract: Various embodiments provide an optimized image filter. The optimized image and video obtains an input image and selects a target pixel for modification. Difference values are then determined between the selected target pixel and each reference pixel of a search area. Subsequently, a weighting function is used to determine weight values for each of the reference pixels of the search area based on their respective difference value. The selected target pixel is then modified by the optimized image filter using the determined weight values. A new target pixel in an apply patch is then selected for modification. The new target pixel is modified using the previously determined weight values reassigned to a new set of reference pixels. The previously determined weight values are reassigned to the new set of reference pixels based on each of the new set of reference pixels' position relative to the new target pixel.

公开(公告)号：US20170288664A1

公开(公告)日：2017-10-05

申请号：US15630469

申请日：2017-06-22

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Alexandre Dray ,  Emmanuel Josse

IPC: H03K17/687 ,  H01L27/02 ,  G01R31/28 ,  H01L21/66

CPC classification number: H03K17/687 ,  G01R31/2884 ,  H01L22/22 ,  H01L22/34 ,  H01L27/0207

Abstract: An integrated circuit includes at least one integrated cell disposed at a location of the integrated circuit. The at least one integrated cell may have two integrated devices coupled to at least one site of the integrated cell and a multiplexer, and the two integrated devices respectively oriented in two different directions of orientation. A first integrated device of the two integrated devices that is oriented in one of the two directions of orientation is usable. The integrated circuit may include a controller configured to detect the direction of orientation which, having regard to the disposition of the integrated cell at the location, may allow the first integrated device to be usable, and to control the multiplexer to couple the first integrated device electrically to the at least one site.

公开(公告)号：US09780015B2

公开(公告)日：2017-10-03

申请号：US15204488

申请日：2016-07-07

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Bar ,  Alisee Taluy ,  Olga Kokshagina

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/36

CPC classification number: H01L23/3675 ,  H01L21/32139 ,  H01L21/4853 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76897 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14519 ,  H01L2224/29013 ,  H01L2224/29082 ,  H01L2224/29111 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/3015 ,  H01L2224/30519 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2224/83801 ,  H01L2224/9211 ,  H01L2924/12042 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83

Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.

公开(公告)号：US20170271777A1

公开(公告)日：2017-09-21

申请号：US15614382

申请日：2017-06-05

Applicant: STMicroelectronics SA

Inventor： Baudouin Martineau ,  Olivier Richard ,  Didier Belot ,  Pierre Dautriche

IPC: H01Q13/06 ,  H01P3/16

CPC classification number: H01Q13/06 ,  H01P3/16 ,  Y10T29/49018 ,  Y10T29/4902

Abstract: A connector for a plastic waveguide includes a connector body having first and second openings aligned with one another. The first opening is configured to receive the plastic waveguide. A radio frequency (RF) antenna is positioned within the second opening of the connector body.

公开(公告)号：US09704903B2

公开(公告)日：2017-07-11

申请号：US14840164

申请日：2015-08-31

Applicant: STMicroelectronics SA

Inventor： Didier Dutartre

IPC: H01L27/14 ,  H01L27/146 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L27/14629 ,  H01L21/7624 ,  H01L21/76264 ,  H01L27/1203 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14689

Abstract: A front-side image sensor may include a substrate in a semiconductor material and an active layer in the semiconductor material. The front side image sensor may also include an array of photodiodes formed in the active layer and an insulating layer between the substrate and the active layer.

公开(公告)号：US09698815B1

公开(公告)日：2017-07-04

申请号：US15237767

申请日：2016-08-16

Applicant: STMicroelectronics SA

Inventor： Mounir Boulemnakher ,  Stephane Le Tual

IPC: H03M1/66 ,  H03M1/12

CPC classification number: H03M1/66 ,  H03M1/124 ,  H03M1/168

Abstract: A multiplying digital to analog converter includes first and second inputs for receiving first and second differential input signals. A differential amplifier has first and second differential input nodes and first and second differential output nodes. A first capacitor is coupled in series with a first switch between the first differential input node and the first input. The first capacitor is further coupled to at least one reference voltage supply node via one or more further switches. A second capacitor is coupled between the first differential input node and the first differential output node. A third capacitor is coupled between the first differential input node and the first input.

公开(公告)号：US09671473B2

公开(公告)日：2017-06-06

申请号：US14286431

申请日：2014-05-23

Applicant: STMicroelectronics SA

Inventor： Severin Trochut ,  Eric Remond

IPC: G01R33/07 ,  H01L43/04 ,  H01L43/06

CPC classification number: G01R33/072 ,  H01L43/04 ,  H01L43/065

Abstract: The generation of a Hall voltage within a semiconductor film of an integrated Hall effect sensor uses the flow of a current within the semiconductor film when subjected to a magnetic field. The film is disposed on top of an insulating layer, referred to as buried layer, which is itself disposed on top of a carrier substrate containing a buried electrode that is situated under the insulating layer. A biasing voltage is applied to the buried electrode.