公开(公告)号：US20200006153A1

公开(公告)日：2020-01-02

申请号：US16052600

申请日：2018-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Kai-Lin Lee ,  Wei-Jen Chen

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8238

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a first gate structure and a second gate structure on the first fin-shaped structure; using a patterned mask to remove the first gate structure and part of the first fin-shaped structure to form a first trench; and forming a first dielectric layer in the first trench to form a first single diffusion break (SDB) structure and around the second gate structure.

公开(公告)号：US20190393099A1

公开(公告)日：2019-12-26

申请号：US16562454

申请日：2019-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/06 ,  H01L27/088 ,  H01L27/12 ,  H01L21/84

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, an isolation structure, and a source/drain region. The semiconductor substrate includes a fin. The gate structure is disposed on the fin and is disposed straddling the fin. The isolation structure covers a sidewall and a top surface of the fin. The source/drain region is disposed in the fin and extends beyond the top surface of the fin.

公开(公告)号：US10515876B1

公开(公告)日：2019-12-24

申请号：US16159789

申请日：2018-10-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Biao Zhou

IPC: H01L21/4763 ,  H01L23/482 ,  H01L23/64 ,  H01L21/768 ,  H01L23/528 ,  H01L21/764 ,  H01L23/522

Abstract: A method for forming a semiconductor device includes: providing a structure having a first stop layer formed above a substrate, a first dielectric layer formed on the first stop layer, a second stop layer formed on the first dielectric layer, and conductive lines formed in the first dielectric layer and spaced apart from each other; forming a first dummy layer on the second stop layer; patterning the first dummy layer to form a first patterned dummy layer; forming a second dummy layer on the first dummy layer to form a first trench; etching back the second dummy layer and the first patterned dummy layer to form a second trench, wherein the second trench is self-aligned with the first trench. The second trench extends downwardly to the first dielectric layer and forms an opening at the second stop layer.

公开(公告)号：US20190384269A1

公开(公告)日：2019-12-19

申请号：US16008114

申请日：2018-06-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Ping YEN ,  Te-Sung HUNG ,  Ming-Kuan KAO ,  Ming-Feng WANG ,  Chieh-Ming CHIU ,  Chin-Hsin HUANG ,  Pin-Kuei LEE ,  Chia-Fan TSAI

IPC: G05B19/418 ,  G06Q10/08

Abstract: A device and a method for analyzing a manufacturing apparatus are provided. The device includes a storing unit, a detecting unit, a calculating unit and a determining unit. The storing unit is for storing a supply amount of material. The detecting unit is for continuously detecting the manufacturing apparatus once the material is used during whole of a process to obtain a total usage. The calculating unit is for calculating a usage ratio of the total usage to the supply amount. The determining unit is for determining whether the manufacturing apparatus is operated in a usage trouble operation according to the usage ratio.

公开(公告)号：US20190362776A1

公开(公告)日：2019-11-28

申请号：US16019521

申请日：2018-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chun-Hsien Huang ,  Hsin-Chih Yu ,  Shu-Ru Wang

IPC: G11C11/412 ,  G11C11/419 ,  H01L43/08 ,  G11C7/12 ,  G11C8/08 ,  H01L43/02 ,  H01L43/10 ,  G01R33/09 ,  H01L27/11

Abstract: A static random access memory (SRAM) structure includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, a second inverter comprising a second pull-up transistor and a second pull-down transistor, a first pass transistor coupled to the first inverter, and a second pass transistor coupled to the second inverter. Preferably, the first inverter is coupled to a first tunnel magnetoresistance (TMR) structure and the second inverter is coupled to a second TMR structure.

公开(公告)号：US20190361339A1

公开(公告)日：2019-11-28

申请号：US15986799

申请日：2018-05-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Pu Chen ,  Shu-Yen Liu ,  Tang-Chun Weng ,  Tuan-Yen Yu

IPC: G03F1/38

Abstract: The present invention provides a photomask, comprising: a substrate, a first region, a second region and a third region are defined thereon, wherein the third region is disposed between the first region and the second region, a patterned layer disposed on the substrate, wherein the patterned layer comprises a first patterned layer disposed in the first region, a second patterned layer disposed in the second region, and a third patterned layer disposed in the third region, and wherein a thickness of the first patterned layer is equal to a thickness of the second patterned layer, the thickness of the first patterned layer is different from a thickness of the third patterned layer, and at least one recess disposed in the third region.

公开(公告)号：US20190355849A1

公开(公告)日：2019-11-21

申请号：US16529523

申请日：2019-08-01

Applicant: United Microelectronics Corp.

Inventor： LING-CHUN CHOU ,  Kun-Hsien Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L27/06 ,  H01L21/8234

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first gate structures, a plurality of second gate structures, a first strained region, and a second strained region. The substrate has a first region and a second region. The first gate structures are disposed in the first region on the substrate. The second gate structures are disposed in the second region on the substrate. The first strained region is formed in the substrate and has a first distance from an adjacent first gate structure. The second strained region is formed in the substrate and has a second distance from an adjacent second gate structure, wherein the second distance is greater than the first distance.

公开(公告)号：US20190355618A1

公开(公告)日：2019-11-21

申请号：US16011615

申请日：2018-06-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a trench in the dielectric layer; forming a first liner in the trench, wherein the first liner comprises Co—Ru alloy; forming a metal layer on the first liner; and planarizing the metal layer and the first liner to form a metal interconnection.

公开(公告)号：US10483158B2

公开(公告)日：2019-11-19

申请号：US16226498

申请日：2018-12-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Hsuan-Tai Hsu ,  Kuan-Hsuan Ku

IPC: H01L21/768 ,  H01L29/417 ,  H01L23/522 ,  H01L21/311 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165

Abstract: A method of fabricating a contact hole structure includes providing a substrate with an epitaxial layer embedded therein. Next, an interlayer dielectric is formed to cover the substrate. After that, a first hole is formed in the interlayer dielectric and the epitaxial layer. Later, a mask layer is formed to cover a sidewall of the first hole and expose a bottom of the first hole. Subsequently, a second hole is formed by etching the epitaxial layer at the bottom of the first hole and taking the mask layer and the interlayer dielectric as a mask, wherein the first hole and the second hole form a contact hole. Then, the mask layer is removed. Finally, a silicide layer is formed to cover the contact hole.

公开(公告)号：US10475903B2

公开(公告)日：2019-11-12

申请号：US16258679

申请日：2019-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ling Wang ,  Ping-Hung Chiang ,  Chang-Po Hsiung ,  Chia-Wen Lu ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L27/088 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/06

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.