公开(公告)号：US20240233244A1

公开(公告)日：2024-07-11

申请号：US18413286

申请日：2024-01-16

Applicant: INTEL CORPORATION

Inventor： Scott JANUS ,  Prasoonkumar SURTI ,  Karthik VAIDYANATHAN ,  Alexey SUPIKOV ,  Gabor LIKTOR ,  Carsten BENTHIN ,  Philip LAWS ,  Michael DOYLE

IPC: G06T15/06 ,  G06T1/60 ,  G06T15/00 ,  G06T17/00

CPC classification number: G06T15/06 ,  G06T1/60 ,  G06T15/005 ,  G06T17/005 ,  G06T2210/21

Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.

公开(公告)号：US20240232056A1

公开(公告)日：2024-07-11

申请号：US18571797

申请日：2021-10-15

Applicant: Intel Corporation

Inventor： Junjun SHAN ,  Yi QIAN ,  Xiangyang WU ,  Qian OUYANG ,  Minggui CAO ,  Junjie MAO ,  Jian Jun CHEN

IPC: G06F11/36

CPC classification number: G06F11/3676 ,  G06F11/3684

Abstract: Examples relate to an apparatus, a device, a method, and a computer program for generating a test specification for testing software code of a function under test. The apparatus for generating the test specification for testing software code of a function under test comprises circuitry configured to extract a plurality of symbols from the software code of the function under test, generate a plurality of test vectors with corresponding sets of expected results for the function under test based on the plurality of symbols, and generate a test specification based on the plurality of test vectors and the corresponding sets of expected results.

公开(公告)号：US20240231839A1

公开(公告)日：2024-07-11

申请号：US18416303

申请日：2024-01-18

Applicant: Intel Corporation

Inventor： Arnab Raha ,  Deepak Mathaikutty ,  Debabrata Mohapatra ,  Sang Kyun Kim ,  Gautham Chinya ,  Cormac Brick

IPC: G06F9/445 ,  G06F9/30 ,  G06F9/50 ,  G06N20/00 ,  H03K19/177 ,  H03K19/20

CPC classification number: G06F9/445 ,  G06F9/3001 ,  G06F9/5027 ,  G06N20/00 ,  H03K19/177 ,  H03K19/20

Abstract: Methods, apparatus, systems, and articles of manufacture to load data into an accelerator are disclosed. An example apparatus includes data provider circuitry to load a first section and an additional amount of compressed machine learning parameter data into a processor engine. Processor engine circuitry executes a machine learning operation using the first section of compressed machine learning parameter data. A compressed local data re-user circuitry determines if a second section is present in the additional amount of compressed machine learning parameter data. The processor engine circuitry executes a machine learning operation using the second section when the second section is present in the additional amount of compressed machine learning parameter data.

公开(公告)号：US20240231454A1

公开(公告)日：2024-07-11

申请号：US18422948

申请日：2024-01-25

Applicant: Intel Corporation

Inventor： Columbia Mishra ,  Carin Ruiz ,  Helin Cao ,  Soethiha Soe ,  James Hermerding, II ,  Bijendra Singh ,  Navneet Singh

IPC: G06F1/20 ,  G06F1/32 ,  G06F3/01 ,  G06V10/774 ,  G06V40/10 ,  G06V40/16 ,  G10L25/51 ,  H04B1/3827

CPC classification number: G06F1/206 ,  G06F1/32 ,  G06F3/013 ,  G06V10/774 ,  G06V40/10 ,  G06V40/165 ,  G10L25/51 ,  H04B1/3827 ,  G06F2200/201

Abstract: Apparatus and methods for thermal management of electronic user devices are disclosed herein. An example apparatus includes at least one of a user presence detection analyzer to identify a presence of a user relative to an electronic device based on first sensor data generated by a first sensor or at least one of an image data analyzer or a motion data analyzer to determine a gesture of the user relative to the device based on second sensor data generated by a second sensor; a thermal constraint selector to select a thermal constraint for a temperature of an exterior surface of the electronic device based on one or more of the presence of the user or the gesture; and a power source manager to adjust a power level for a processor of the electronic device based on the thermal constraint.

公开(公告)号：US12034736B2

公开(公告)日：2024-07-09

申请号：US17484330

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Marcio Juliato ,  Javier Perez-Ramirez ,  Mikhail Galeev ,  Christopher Gutierrez ,  Dave Cavalcanti ,  Manoj Sastry ,  Vuk Lesi

IPC: H04L29/06 ,  H04L9/06 ,  H04L9/40 ,  H04L69/22 ,  H04L69/28

CPC classification number: H04L63/105 ,  H04L9/0656 ,  H04L63/1483 ,  H04L69/22 ,  H04L69/28

Abstract: Systems and methods to detect attacks on the clocks of devices in time sensitive networks are described. Particularly, the disclosed systems and methods provide detection and mitigation of timing synchronization attacks based on pseudo-random numbers generated and used to select and authenticate timing of transmission of messages in protected transmission windows.

公开(公告)号：US12034452B2

公开(公告)日：2024-07-09

申请号：US17132000

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Daniel Gruber ,  Michael Kalcher ,  Martin Clara

IPC: H03M1/72 ,  H04B1/04 ,  H04W88/08

CPC classification number: H03M1/72 ,  H04B1/04 ,  H04W88/08

Abstract: A Digital-to-Analog Converter (DAC) is provided. The DAC includes a code converter circuit configured to sequentially receive first digital control codes for controlling N digital-to-analog converter cells. N is an integer greater than one. The code converter circuit is further configured to convert the first digital control codes to second digital control codes. Additionally, the DAC includes a bit-shifter circuit configured to receive shift codes for the second digital control codes. The shift codes are obtained using dynamic element matching and indicate a respective circular shift by ri bit positions for the i-th second digital control code, wherein ri is an integer smaller than N−1. The bit-shifter circuit is further configured to generate third digital control codes by circularly shifting the second digital codes based on the shift codes. In addition, the DAC includes a cell activation circuit configured to selectively activate one or more of the N digital-to-analog converter cells based on the third digital control codes.

公开(公告)号：US12033302B2

公开(公告)日：2024-07-09

申请号：US17435653

申请日：2019-06-21

Applicant: Intel Corporation

Inventor： Wenyi Tang ,  Xu Zhang

IPC: G06T3/4046 ,  G06N3/047 ,  G06T3/4053

CPC classification number: G06T3/4053 ,  G06N3/047 ,  G06T3/4046

Abstract: Embodiments described herein are generally directed to an end-to-end trainable degradation restoration network (DRN) that enhances the ability of a super-resolution (SR) subnetwork to deal with noisy low-resolution images. An embodiment of a method includes estimating, by a noise estimator (NE) subnetwork of the DRN, an estimated noise map for a noisy input image; and predicting, by the SR subnetwork of the DRN, a clean upscaled image based on the input image and the noise map by, for each of multiple conditional residual dense blocks (CRDBs) stacked within one or more cascade blocks representing the SR subnetwork, adjusting, by a noise control layer of the CRDB that follows a stacked set of a multiple residual dense blocks of the CRDB, feature values of an intermediate feature map associated with the input image by applying (i) a scaling factor and (ii) an offset factor derived from the noise map.

公开(公告)号：US12033000B2

公开(公告)日：2024-07-09

申请号：US17201635

申请日：2021-03-15

Applicant: Intel Corporation

Inventor： Shao-Wen Yang

IPC: G06F9/50 ,  G06F9/48 ,  H04L41/0806 ,  H04L41/0896 ,  H04L41/12

CPC classification number: G06F9/5038 ,  G06F9/4881 ,  G06F9/505 ,  G06F9/5072 ,  H04L41/0806 ,  H04L41/0896 ,  H04L41/12 ,  G06F2209/5017 ,  G06F2209/506

Abstract: In one embodiment, an apparatus comprises a communication interface to communicate over a network, and a processor. The processor is to: receive a workload provisioning request from a user, wherein the workload provisioning request comprises information associated with a workload, a network topology, and a plurality of potential hardware choices for deploying the workload over the network topology; receive hardware performance information for the plurality of potential hardware choices from one or more hardware providers; generate a task dependency graph associated with the workload; generate a device connectivity graph associated with the network topology; select, based on the task dependency graph and the device connectivity graph, one or more hardware choices from the plurality of potential hardware choices; and provision a plurality of resources for deploying the workload over the network topology, wherein the plurality of resources are provisioned based on the one or more hardware choices.

公开(公告)号：US12032890B2

公开(公告)日：2024-07-09

申请号：US16928975

申请日：2020-07-14

Applicant: Intel Corporation

Inventor： Sergei Babokhov ,  Charles Magnuson

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  G06F3/04847 ,  G06F117/10

CPC classification number: G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  G06F3/04847 ,  G06F2117/10

Abstract: A method to place repeaters on existing structured routes based on user specified locations. Location can be specified in multiple ways. For example, a set of fixed repeating distances (starting from a driver), number of repeaters (spread evenly on net routing), an absolute cutline dissecting the existing nets routing (e.g., x or y coordinate measure from the origin of the cell), relative cutline dissecting the existing nets routing (e.g., x or y coordinate measured from the origin of the nets bounding box), etc. can specify location. A repeater legalization procedure allows a user to arrange repeaters in various forms thus legalizing them to meet specific design requirements. A preview mode is provided where results are presented in the form of annotations (e.g., cartoon drawings) displayed on a canvas (e.g., display screen) rather than in the form of real layout objects in a database.

公开(公告)号：US20240224463A1

公开(公告)日：2024-07-04

申请号：US18147522

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Ali Kalantarian ,  Saanjali Maharaj ,  Tejas Shah ,  Tamara Low Foon ,  Mirui Wang

IPC: H05K7/20 ,  G06F1/20

CPC classification number: H05K7/20209 ,  G06F1/206 ,  H05K7/20154 ,  H05K7/20172

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example system includes interface circuitry; first programmable circuitry; and instructions to cause the first programmable circuitry to: determine, based on a first signal output by a first sensor, a first temperature at a first location that is associated with second programmable circuitry; determine, based on a second signal output by a second sensor, a second temperature at a second location that is different than the first location; set a first thermal setpoint for the second programmable circuitry in response to the second temperature failing to satisfy a threshold value; and set a second thermal setpoint for the second programmable circuitry in response to the second temperature satisfying the threshold value, wherein the second thermal setpoint is higher than the first thermal setpoint.