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公开(公告)号：US09298609B2
公开(公告)日：2016-03-29
申请号：US14280437
申请日：2014-05-16
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Ely K. Tsern
CPC classification number: G06F12/0253 , G06F12/0246 , G06F12/08 , G06F12/0802 , G06F12/0804 , G06F12/0891 , G06F12/1009 , G06F2212/1036 , G06F2212/2022 , G06F2212/60 , G06F2212/7201 , G06F2212/7205 , G06F2212/7211
Abstract: A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.
Abstract translation: 存储器系统包括表现出与写入操作不对称的磨损机制的非易失性物理存储器，例如闪速存储器。 易失性存储器的相对较小的缓存减少了写入次数，并且磨损均衡的存储器访问方法将写入均匀地分布在非易失性存储器上。
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公开(公告)号：US09257163B2
公开(公告)日：2016-02-09
申请号：US13959633
申请日：2013-08-05
Applicant: Rambus Inc.
Inventor： Bret Stott , Frederick A. Ware , Ian P. Shaeffer , Yuanlong Wang
CPC classification number: G11C7/222 , G06F13/1689 , G11C7/02 , G11C7/22
Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.
Abstract translation: 存储器控制器包括用于接收数据选通信号和对应的读取数据的接口。 数据选通信号和读取数据对应于由存储器控制器发出的读取命令，并且根据数据选通信号和使能信号接收读取的数据。 存储器控制器中的电路是动态地调整使能信号和数据选通信号之间的定时偏移，并且控制逻辑将根据从自由信号发出的最后读取命令以来的时间间隔的确定发出补充读取命令 存储器控制器超过预定值。
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公开(公告)号：US20160004594A1
公开(公告)日：2016-01-07
申请号：US14853888
申请日：2015-09-14
Applicant: Rambus Inc.
Inventor： Yuanlong Wang , Frederick A. Ware
CPC classification number: G06F11/0727 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/073 , G06F11/0751 , G06F11/076 , G06F11/0793 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1044 , G06F11/1068 , G06F11/1402 , G06F13/4286 , H03M13/09 , H03M13/29 , H03M13/2906 , H03M13/611 , H04L1/0003 , H04L1/0008 , H04L1/0061 , H04L1/08 , H04L1/1867 , H04L2001/0093
Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
Abstract translation: 控制器包括要耦合到第一链路以传送双向数据的链路接口和用于发送单向错误检测信息的第二链路。 编码器将动态地将第一错误检测信息添加到写入数据的至少一部分。 耦合到链路接口的发射机是发送写入数据。 延迟元件耦合到编码器的输出。 耦合到链路接口的接收机是接收对应于写数据的至少一部分的第二错误检测信息。 错误检测逻辑耦合到来自延迟元件的输出和来自接收器的输出。 错误检测逻辑是通过比较第一错误检测信息和第二错误检测信息来确定写入数据的至少一部分中的错误，并且如果检测到错误则是断言错误状况。
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公开(公告)号：US20160004593A1
公开(公告)日：2016-01-07
申请号：US14853869
申请日：2015-09-14
Applicant: Rambus Inc.
Inventor： Yuanlong Wang , Frederick A. Ware
CPC classification number: G06F11/0727 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/073 , G06F11/0751 , G06F11/076 , G06F11/0793 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1044 , G06F11/1068 , G06F11/1402 , G06F13/4286 , H03M13/09 , H03M13/29 , H03M13/2906 , H03M13/611 , H04L1/0003 , H04L1/0008 , H04L1/0061 , H04L1/08 , H04L1/1867 , H04L2001/0093
Abstract: A controller includes a link interface that is to couple to a first link to communicate bidirectional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
Abstract translation: 控制器包括要耦合到第一链路以传送双向数据的链路接口和用于发送单向错误检测信息的第二链路。 编码器将动态地将第一错误检测信息添加到写入数据的至少一部分。 耦合到链路接口的发射机是传输写入数据。 延迟元件耦合到编码器的输出。 耦合到链路接口的接收机是接收对应于写数据的至少一部分的第二错误检测信息。 错误检测逻辑耦合到来自延迟元件的输出和来自接收器的输出。 错误检测逻辑是通过比较第一错误检测信息和第二错误检测信息来确定写入数据的至少一部分中的错误，并且如果检测到错误则是断言错误状况。
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655.发明申请公开(公告)号：US20150363107A1
公开(公告)日：2015-12-17
申请号：US14737147
申请日：2015-06-11
Applicant: Rambus Inc.
Inventor： Scott C. Best , Frederick A. Ware , William N. Ng
CPC classification number: G11C7/1093 , G11C5/04 , G11C7/1003 , G11C7/1066
Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.
Abstract translation: 存储器模块可以被编程为在第一访问模式下提供相对宽的，低延迟的数据，或者在第二访问模式中牺牲一些延迟，以换取较窄的数据宽度，较窄的命令宽度或两者。 窄的，更高延迟的模式需要更少的连接和跟踪。 因此，控制器可以支持更多的模块，从而增加系统容量。 因此可编程模块允许计算机制造商在存储器延迟，容量和成本之间达到期望的平衡。
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Patent Agency Ranking
公开(公告)号：US20150357002A1
公开(公告)日：2015-12-10
申请号：US14827831
申请日：2015-08-17
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Paul D. Franzon
CPC classification number: G11C5/02 , G11C7/22 , G11C11/4076 , G11C29/80 , G11C29/808 , G11C2213/71 , H01L23/5384 , H01L2924/0002 , H01L2924/00
Abstract: A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations. Redundant storage is provided including a first storage area dedicated to storing failure address information of failure address locations in the first or second integrated circuit memory chips. The redundant storage includes a second storage area dedicated to storing data corresponding to the failure address locations. Matching logic matches incoming data transfer addresses to the stored failure address information.
Abstract translation: 公开了一种堆叠存储器，其包括具有第一存储位置的第一集成电路存储器芯片和与第一集成电路存储器芯片堆叠关系地设置的第二集成电路存储器芯片。 第二集成电路存储器芯片具有第二存储位置。 提供了冗余存储器，其包括专用于存储第一或第二集成电路存储器芯片中的故障地址位置的故障地址信息的第一存储区域。 冗余存储器包括专用于存储对应于故障地址位置的数据的第二存储区域。 匹配逻辑将输入的数据传输地址与存储的故障地址信息进行匹配。
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公开(公告)号：US20150268862A1
公开(公告)日：2015-09-24
申请号：US14441810
申请日：2013-11-26
Applicant: RAMBUS INC.
Inventor： Frederick A. Ware , John Eric Linstadt
IPC: G06F3/06
CPC classification number: G06F3/0604 , G06F3/0635 , G06F3/0673 , G06F12/06 , G06F2212/1048 , G11C8/12 , G11C2207/107
Abstract: A multiple memory rank selection method and system assigns, based at least in part on decoding an assignment signal in a second command/address signal, a first terminal of a memory device to receive a first command/address signal and a second terminal of the memory device to receive the second command/address signal or assigns the first terminal of the memory device to receive the second command/address signal and the second terminal of the memory device to receive the first command/address signal. The multiple memory selection method and system decodes a selection signal encoded in the first command/address signal and enables the memory device based at least in part on the assignment signal and the selection signal.
Abstract translation: 多存储器等级选择方法和系统至少部分地基于对第二命令/地址信号中的分配信号的解码来分配存储器件的第一端子，以接收第一命令/地址信号和存储器的第二端子 用于接收第二命令/地址信号或分配存储器件的第一端以接收第二命令/地址信号和存储器件的第二端以接收第一命令/地址信号。 多存储器选择方法和系统解码在第一命令/地址信号中编码的选择信号，并且至少部分地基于分配信号和选择信号使存储器件能够使能。
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658.发明授权Memory component with pattern register circuitry to provide data patterns for calibration 有权具有模式寄存器电路的存储器组件，用于提供用于校准的数据模式公开(公告)号：US09123433B2
公开(公告)日：2015-09-01
申请号：US13949982
申请日：2013-07-24
Applicant: Rambus Inc.
Inventor： Craig E. Hampel , Richard E. Perego , Stefanos Sidiropoulos , Ely K. Tsern , Frederick A. Ware
IPC: G11C7/22 , G11C11/406 , G11C7/10 , G11C11/4078 , G06F12/02 , G11C21/00 , H04L7/00
CPC classification number: G11C11/4076 , G06F3/061 , G06F3/0629 , G06F3/0671 , G06F12/0246 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/222 , G11C11/40611 , G11C11/4072 , G11C11/4078 , G11C11/4093 , G11C21/00 , G11C2207/2254 , H04L7/0025 , H04L7/0079 , H04L7/0091
Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration.
Abstract translation: 存储器组件包括包含动态随机存取存储器（DRAM）存储单元的存储器核心和用于接收外部命令的第一电路。 外部命令包括指定发送从存储器核心访问的数据的读取命令。 存储器组件还包括响应于读取命令和在校准期间可操作以提供至少第一数据模式和第二数据模式的读取命令和模式寄存器电路将数据发送到外部总线的第二电路。 在校准期间，第一数据模式和第二数据模式中的所选择的一个被响应于在校准期间接收到的读命令，被第二电路发送到外部总线上。
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公开(公告)号：US20150234738A1
公开(公告)日：2015-08-20
申请号：US14566411
申请日：2014-12-10
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Craig E. Hampel
IPC: G06F12/02
CPC classification number: G06F12/02 , G06F12/0292
Abstract: Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK′ and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.
Abstract translation: 公开了用于“调平”或平均化更多地平均化由存储器组件的行看到的激活/预充电循环的数量的改进，使得一个或多个特定行不会被过度压缩（相对于其他行）。 在一个实施例中，存储器控制器包括重新配置设备，用于将存储在物理行中的数据从RPK移动到RPK，并修改来自逻辑行RLK的映射，同时最小化对正常读/写操作的影响。 可以相对于刷新或其他维护操作调度重新映射操作。 重新映射操作可以有条件地推迟，以便最小化性能影响。
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公开(公告)号：US09092352B2
公开(公告)日：2015-07-28
申请号：US14175955
申请日：2014-02-07
Applicant: Rambus Inc.
Inventor： Yuanlong Wang , Frederick A. Ware
CPC classification number: G06F11/0727 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/073 , G06F11/0751 , G06F11/076 , G06F11/0793 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1044 , G06F11/1068 , G06F11/1402 , G06F13/4286 , H03M13/09 , H03M13/29 , H03M13/2906 , H03M13/611 , H04L1/0003 , H04L1/0008 , H04L1/0061 , H04L1/08 , H04L1/1867 , H04L2001/0093
Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
Abstract translation: 控制器包括要耦合到第一链路以传送双向数据的链路接口和用于发送单向错误检测信息的第二链路。 编码器将动态地将第一错误检测信息添加到写入数据的至少一部分。 耦合到链路接口的发射机是发送写入数据。 延迟元件耦合到编码器的输出。 耦合到链路接口的接收机是接收对应于写数据的至少一部分的第二错误检测信息。 错误检测逻辑耦合到来自延迟元件的输出和来自接收器的输出。 错误检测逻辑是通过比较第一错误检测信息和第二错误检测信息来确定写入数据的至少一部分中的错误，并且如果检测到错误则是断言错误状况。
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