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671.发明授权公开(公告)号：US10049237B2
公开(公告)日：2018-08-14
申请号：US15473074
申请日：2017-03-29
Applicant: STMicroelectronics International N.V
Inventor： Kosta Kovacic , Albin Pevec , Maksimiljan Stiglic
Abstract: Embodiments provide a method for sending a message from an RFID transponder to a reader during a transmission frame using active load modulation, the method comprising. An encoded bit signal has a first logic level during first time segments within the transmission frame and a second logic level during second time segments within the transmission frame. The first time segments include an initial time segment of the transmission frame. A transmission signal is generated based on the encoded bit signal. The transmission signal is generated having a first phase depending on the first logic level during the first time segments, a second phase depending on the second logic level during the second time segments, and the second phase during a time interval preceding the transmission frame.
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公开(公告)号：US10037794B1
公开(公告)日：2018-07-31
申请号：US15660371
申请日：2017-07-26
Applicant: STMicroelectronics International N.V.
Inventor： Dhori Kedar Janardan , Abhishek Pathak , Shishir Kumar
IPC: G11C5/06 , G11C11/417
CPC classification number: G11C11/417 , G11C5/14 , G11C7/227 , G11C11/419 , G11C2207/002
Abstract: A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.
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公开(公告)号：US10024888B2
公开(公告)日：2018-07-17
申请号：US15618269
申请日：2017-06-09
Applicant: STMicroelectronics International N.V.
Inventor： Daljeet Kumar , Tapas Nandy , Surendra Kumar
Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.
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公开(公告)号：US20180189642A1
公开(公告)日：2018-07-05
申请号：US15423284
申请日：2017-02-02
Inventor： Thomas BOESCH , Giuseppe DESOLI
Abstract: Embodiments are directed towards a configurable accelerator framework device that includes a stream switch and a plurality of convolution accelerators. The stream switch has a plurality of input ports and a plurality of output ports. Each of the input ports is configurable at run time to unidirectionally pass data to any one or more of the output ports via a stream link. Each one of the plurality of convolution accelerators is configurable at run time to unidirectionally receive input data via at least two of the plurality of stream switch output ports, and each one of the plurality of convolution accelerators is further configurable at run time to unidirectionally communicate output data via an input port of the stream switch.
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公开(公告)号：US10008258B2
公开(公告)日：2018-06-26
申请号：US15296567
申请日：2016-10-18
Applicant: STMicroelectronics International N.V
Inventor： Piyush Jain , Vivek Asthana , Naveen Batra
IPC: G11C11/419 , G11C7/12 , G11C5/14
CPC classification number: G11C11/419 , G11C5/14 , G11C7/12
Abstract: A circuit can be used, for example, with a multi-supply memory device. The circuit includes a first conductor and a second conductor. A first transistor has a current path coupled between the first conductor and the second conductor. A second transistor also has a current path coupled between the first conductor and the second conductor. A pulse generator circuit has an input coupled to a control terminal of the first transistor and an output coupled to a control terminal of the second transistor.
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Patent Agency Ranking
公开(公告)号：US20180166128A1
公开(公告)日：2018-06-14
申请号：US15375987
申请日：2016-12-12
Applicant: STMicroelectronics International N.V.
Inventor： Harsh Rawat , Abhishek Pathak
IPC: G11C11/419 , G11C11/418 , G06F1/06 , G06F13/16
CPC classification number: G11C11/419 , G06F1/06 , G06F13/1689 , G11C7/1075 , G11C8/16 , G11C11/413 , G11C11/418
Abstract: A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.
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公开(公告)号：US20180159544A1
公开(公告)日：2018-06-07
申请号：US15888153
申请日：2018-02-05
Applicant: STMicroelectronics International N.V.
Inventor： Anand Kumar , Gagan Midha
CPC classification number: H03L7/093 , H03C3/095 , H03L7/0891 , H03L7/099 , H03L7/1976 , H04B15/04
Abstract: A phase or frequency locked-loop circuit includes an oscillator configured to generate an output clock signal having a frequency set by an oscillator control signal. A modulator circuit receives a first signal and a second signal and is configured to generate a control signal having a value modulated in response to the first and second signals. A filter circuit generates the oscillator control signal by filtering the control signal. A delta-sigma modulator circuit operates to modulate the second signal in response to a modulation profile. As a result, the output clock signal is a spread spectrum clock signal.
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公开(公告)号：US20180129239A1
公开(公告)日：2018-05-10
申请号：US15866651
申请日：2018-01-10
Applicant: STMicroelectronics International N.V.
Inventor： Abhirup Lahiri
Abstract: A reference voltage generator circuit includes a circuit that generates a complementary to absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) current. An output current circuit generates, from the PTAT current, a sink PTAT current sunk from a first node and a source PTAT current sourced to a second node, wherein the sink and source PTAT currents are equal. A resistor is directly connected between the first node and the second node. A divider circuit divides the CTAT voltage to generate a divided CTAT voltage applied to the first node. A voltage at the second node is a fractional bandgap reference voltage equal to a sum of the divided CTAT voltage and a voltage drop across the resistor that is proportional to a resistor current equal to the sink and source PTAT currents.
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公开(公告)号：US20180109266A1
公开(公告)日：2018-04-19
申请号：US15297537
申请日：2016-10-19
Applicant: STMicroelectronics International N.V.
Inventor： Nitin Gupta , Jeet Narayan Tiwari
CPC classification number: H03L7/1974 , H03K19/20 , H03K21/00 , H03K21/10 , H03K23/00 , H03K23/667 , H03K23/68 , H03K23/70
Abstract: In accordance with an embodiment, a circuit includes an input clock terminal, an output clock terminal, a first input data terminal, and a set of input data terminals having a number of terminals. A divide-by-two block is coupled to the output clock terminal. A modular one-shot clock divider is coupled between the input clock terminal and the divide-by-two block. The modular one-shot clock divider is further coupled to the set of input data terminals. An intermediate clock generation block is coupled between the input clock terminal and the modular one-shot clock divider. The intermediate clock generation block includes a first digital logic block coupled between the input clock terminal and the modular one-shot clock divider. The first digital logic block is further coupled to the first input data terminal, and a clock-blocking block is coupled between the divide-by-two block and the first digital logic block.
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公开(公告)号：US09948752B2
公开(公告)日：2018-04-17
申请号：US14611343
申请日：2015-02-02
Applicant: STMicroelectronics International N.V.
Inventor： Minh Tri Do Khac
IPC: H04L29/06 , H04W4/00 , H04L12/781 , H04L12/725 , H04L12/741
CPC classification number: H04L69/22 , H04L45/306 , H04L45/52 , H04L45/74 , H04W4/80
Abstract: A method includes receiving a data packet transmitted by a near field communications (NFC) device at a NFC controller. Whether the data packet includes application identifier routing information is determined, and based thereupon the data packet is routed to a default application identifier routing address based on a look-up table lacking an application identifier routing address associated with the application identifier routing information. Whether the data packet includes protocol routing information is determined based upon the data packet lacking the application identifier routing information, and the data packet is routed to a default protocol routing address based upon the look-up table lacking a protocol routing address associated with the protocol routing information, using the NFC controller. The default application identifier routing address is different than the default protocol routing address.
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