公开(公告)号：US5392412A

公开(公告)日：1995-02-21

申请号：US770695

申请日：1991-10-03

Applicant: James L. McKenna

Inventor： James L. McKenna

IPC: G06F5/10 ,  G06F13/16 ,  H04L29/06 ,  G06F12/00 ,  G06F13/00 ,  H04J3/24

CPC classification number: G06F5/10 ,  G06F13/16 ,  H04L29/06

Abstract: A data communication controller having a memory access control unit characterized by a symmetrical access port architecture. The memory access control unit allows both a host processor and the medium access control (MAC) unit of the data communication controller to transparently access a single-port data packet buffer memory while operating at full specified operating speed and without interference between simultaneous memory access requests. The memory access control unit arbitrates asynchronous memory access requests from both the host processor and the medium access control unit, while permitting each of these processors unlimited access to the single-port buffer memory as if it alone had the full memory available to itself at all times. The above capabilities are achieved using automatic address incrementation and data-byte prefetching operations, without requiring the use of a port processor or additional internal data buses.

Abstract translation: 一种具有存储器访问控制单元的数据通信控制器，其特征在于对称接入端口架构。 存储器访问控制单元允许数据通信控制器的主机处理器和介质访问控制（MAC）单元在完全指定的操作速度下工作时透明地访问单端口数据包缓冲存储器，并且在同时存储器访问请求之间没有干扰 。 存储器访问控制单元仲裁来自主机处理器和介质访问控制单元的异步存储器访问请求，同时允许这些处理器中的每一个对单端口缓冲存储器进行无限制的访问，就好像单独存在完全可用的存储器一样 次 上述功能使用自动地址递增和数据字节预取操作来实现，而不需要使用端口处理器或附加的内部数据总线。

公开(公告)号：US5216299A

公开(公告)日：1993-06-01

申请号：US835207

申请日：1992-02-13

Applicant: Frank M. Wanlass

Inventor： Frank M. Wanlass

IPC: H03K19/0185 ,  H03K3/012 ,  H03K3/013 ,  H03K3/356 ,  H03K19/003

CPC classification number: H03K3/356017 ,  H03K3/012 ,  H03K3/013 ,  H03K3/356113

Abstract: A lower power, noise rejecting TTL-to-CMOS input buffer, without the use of a current consuming voltage reference, has the characteristic of recognizing a logic LOW as less than 0.8 volts and a logic HIGH as greater than 2.0 volts for DC TTL signals while drawing only leakage current from its Vcc power supply, and simultaneously possesses the characteristic of rejecting high-amplitude Vin noise. For an input signal rapidly rising from zero to three volts, the buffer output switches at an input signal level of approximately 2.5 volts; and for the input signal rapidly falling from 3 to zero volts, the buffer output switches at an input signal level of approximately 1.4 volts.

Abstract translation: 低功耗，噪声抑制的TTL至CMOS输入缓冲器，不使用电流消耗电压基准，具有将逻辑低电平识别为小于0.8伏的特性，并且对于DC TTL信号具有大于2.0伏特的逻辑高电平 同时从Vcc电源中只吸收漏电流，同时具有抑制高振幅Vin噪声的特点。 对于输入信号从零快速上升到三伏，缓冲器输出在大约2.5伏特的输入信号电平处切换; 并且对于输入信号从3伏快速下降至零伏特，缓冲器输出在大约1.4伏特的输入信号电平处切换。

公开(公告)号：US4908326A

公开(公告)日：1990-03-13

申请号：US291492

申请日：1988-12-29

Applicant: Di Ma ,  David H. Hoffman

Inventor： Di Ma ,  David H. Hoffman

IPC: H01L21/033 ,  H01L21/336 ,  H01L21/60

CPC classification number: H01L21/28518 ,  H01L21/0337 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66598 ,  H01L29/665 ,  Y10S257/90

Abstract: In a method for fabricating an MOS structure, in accordance with one embodiment, a layer of material that serves as an etching stop during the side wall spacer etch, is inserted between the silicon substrate and the side wall spacer. In another embodiment of the invention, after establishing differential layer thicknesses on the source/drain surface, the side wall spacer is completely removed and light and heavy ion implantation steps are performed sequentially with one single lithographic step. In a further embodiment of the invention, after the self-aligned silicide is formed, the side wall spacer is removed, and light and heavy ion implantation steps are sequentially performed.

Abstract translation: 在制造MOS结构的方法中，根据一个实施例，在硅衬底和侧壁间隔物之间​​插入用作侧壁间隔物蚀刻期间的蚀刻停止层的材料层。 在本发明的另一个实施例中，在源极/漏极表面上建立差分层厚度之后，完全去除侧壁间隔物，并且通过一个单一光刻步骤顺序地执行轻重离子注入步骤。 在本发明的另一实施例中，在形成自对准硅化物之后，去除侧壁间隔物，并且顺序地进行轻重离子注入步骤。

公开(公告)号：US4895520A

公开(公告)日：1990-01-23

申请号：US305959

申请日：1989-02-02

Applicant: John E. Berg

Inventor： John E. Berg

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/336

CPC classification number: H01L29/66583 ,  H01L21/28035 ,  H01L29/66537 ,  Y10S148/141

Abstract: A method is disclosed for fabricating submicron silicon gate metal-oxide-semiconductor field effect transistors (MOSFETs) which have threshold and punchthrough implants that are self-aligned to the gate electrode and source and drain regions. A layer of dielectric material (12) is either deposited or grown on the surface of a substrate, and a trench (15), which defines the region of the MOSFET gate electrode, is formed in the dielectric layer. A gate oxide (16) is formed at the exposed substrate at the bottom of the trench, and an implant is performed into the silicon substrate wherever there is gate oxide, but not into the portion of the substrate covered by the original dielectric layer. A layer of polysilicon (20), preferably doped, or another metallic film is then deposited onto the surface. The polysilicon is etched back to the top surface of the dielectric layer, thereby leaving polysilicon in the trench to form the gate electrode (24). The dielectric layer (12) is then etched back preferentially to a thickness approximately equal to the thickness of the gate dielectric, and a high-dose implant is performed through the reduced thickness dielectric layer into the silicon substrate, except for the areas covered by the polysilicon gate to form the source and drain regions (30) of the MOSFET.

Abstract translation: 公开了一种用于制造亚微米硅栅极金属氧化物半导体场效应晶体管（MOSFET）的方法，其具有与栅极电极和源极和漏极区域自对准的阈值和穿通植入物。 在衬底的表面上沉积或生长介电材料层（12），并且在电介质层中形成限定MOSFET栅电极的区域的沟槽（15）。 栅极氧化物（16）形成在沟槽底部的暴露的衬底处，并且在存在栅极氧化物的地方进行硅衬底中的注入，但不进入由原始介电层覆盖的衬底的部分中的注入。 然后将一层优选掺杂的多晶硅（20）或另一种金属膜沉积在该表面上。 多晶硅被蚀刻回到介电层的顶表面，从而在沟槽中留下多晶硅以形成栅电极（24）。 然后将电介质层（12）优先回蚀刻到大致等于栅极电介质厚度的厚度，并且通过减小厚度的介电层进行高剂量注入到硅衬底中，除了由 多晶硅栅极，以形成MOSFET的源极和漏极区域（30）。

公开(公告)号：US4775864A

公开(公告)日：1988-10-04

申请号：US894035

申请日：1986-08-07

Applicant: Morton B. Herman

Inventor： Morton B. Herman

IPC: H04L12/40 ,  H04Q9/00 ,  H04B1/40 ,  H04J3/00 ,  H04L5/14

CPC classification number: H04L12/4625 ,  H04L12/40045 ,  H04L12/417

Abstract: In a local area network, a plurality of nodes are connected to a single port of a hub through a length of cable and a corresponding plurality of transceivers attached to the cable, each of the transceivers having an output impedance significantly greater than the cable characteristic impedance, thereby allowing a plurality of nodes to be connected to one hub port with a single cable.

Abstract translation: 在局域网中，多个节点通过电缆长度连接到集线器的单个端口，并且相应的多个收发器连接到电缆，每个收发器具有显着大于电缆特性阻抗的输出阻抗 ，从而允许多个节点通过单个电缆连接到一个集线器端口。

公开(公告)号：US4764484A

公开(公告)日：1988-08-16

申请号：US107572

申请日：1987-10-08

Applicant: Roy Mo

Inventor： Roy Mo

IPC: H01L21/3205 ,  H01L21/768 ,  H01L21/88 ,  H01L21/302

CPC classification number: H01L21/76879 ,  Y10S148/02 ,  Y10S148/106

Abstract: A method is disclosed for fabricating a VLSI multilevel metallization integrated circuit in which a first dielectric layer (10), a thin silicon layer (16), and then a second dielectric layer (18) are deposited on the upper surface of a substrate. A trench (20) is formed in the upper, second dielectric layer leaving a thin layer of the second dielectric layer overlying the thin silicon layer. A contact hole (26) is then etched through the central part of the thin layer of the second dielectric layer, the thin silicon layer and the first dielectric layer to the surface of the substrate. Using the remaining outer portion (24a) of the thin layer of the dielectric layer as a mask over the underlying portion of the thin silicon layer, metal (28) such as tungsten is selectively deposited into the contact hole. The remaining portion of the thin layer of the second dielectric layer is then removed and the trench is selectively filled with a metal that is in electrical contact with the metal filling the contact hole.

Abstract translation: 公开了一种用于制造VLSI多层金属化集成电路的方法，其中第一介电层（10），薄硅层（16），然后第二介电层（18）沉积在衬底的上表面上。 沟槽（20）形成在上，第二电介质层中，留下覆在薄硅层上的第二电介质层的薄层。 然后，将接触孔（26）通过第二电介质层的薄层的中心部分，薄硅层和第一介电层蚀刻到衬底的表面。 使用电介质层的薄层的剩余的外部部分（24a）作为薄硅层下面的掩模，金属（28）如钨被选择性地沉积到接触孔中。 然后去除第二电介质层的薄层的剩余部分，并且沟槽选择性地填充有与填充接触孔的金属电接触的金属。

公开(公告)号：US4600933A

公开(公告)日：1986-07-15

申请号：US49916

申请日：1979-06-19

Applicant: Paul Richman

Inventor： Paul Richman

IPC: H01L21/265 ,  H01L21/8236 ,  H01L21/8246 ,  H01L29/78

CPC classification number: H01L27/1126 ,  H01L21/265 ,  H01L21/8236

Abstract: An integrated circuit structure includes a substrate, diffused regions formed in the upper surface of the substrate, and thin and thick insulative regions, polycrystalline regions, and metallic interconnections selectively formed overlying selected areas of the substrate surface. An insulating passivation layer overlying the integrated circuit provides mechanical protection for the integrated circuit. Openings are selectively formed in the passivation layer overlying a portion of the integrated circuit at a position other than that of a bonding pad, and above one of the polycrystalline regions positioned over one of the thin insulating regions. The openings may be used to perform ion implantation to modify theelectrical characteristics, such as the threshold voltage, of the integrated circuit at those locations. The disturbance produced in the lattice structure of the silicon substrate during selective ion implantation may, in one aspect of the invention, not be annealed out in subsequent processing steps such that the remaining lattice disturbance further modifies the threshold voltage at the selected implanted locations.

Abstract translation: 集成电路结构包括衬底，形成在衬底的上表面中的扩散区，以及选择性地形成在衬底表面的选定区域上的薄而厚的绝缘区域，多晶区域和金属互连。 覆盖集成电路的绝缘钝化层为集成电路提供机械保护。 选择性地在钝化层中形成开口，所述钝化层覆盖在不同于焊盘的位置处的集成电路的一部分上方，并且位于位于薄绝缘区之一上的多晶区域之上。 这些开口可用于执行离子注入以修改在那些位置处的集成电路的电特性，例如阈值电压。 在本发明的一个方面，在选择性离子注入期间在硅衬底的晶格结构中产生的干扰在后续处理步骤中不被退火，使得剩余的晶格扰动进一步修改所选择的注入位置处的阈值电压。

公开(公告)号：US4433253A

公开(公告)日：1984-02-21

申请号：US329591

申请日：1981-12-10

Applicant: John M. Zapisek

Inventor： John M. Zapisek

IPC: G05F3/20 ,  H03K5/15 ,  H03L5/00 ,  H03K17/687

CPC classification number: G05F3/205 ,  H03K5/15013

Abstract: An internal bias generator for providing a negative bias voltage to the substrate of an MOS integrated circuit at a magnitude higher than the power supply voltage includes a pump circuit which comprises a plurality of switches which are sequentially actuated by nonoverlapping clock signals to alternately charge and discharge a capacitor. The clock signals are produced by a generator which includes a series of RC-delay inverting amplifier stages coupled to a series of NOR gates. The bias generator further comprises a threshold-sensitive regulator which uses the source-body effect of substrate bias on the threshold voltage of an MOS FET to control the magnitude of the applied bias voltage. When the sensed threshold voltage deviates from a desired level, certain of the clock signals are disabled, thereby to modify the bias voltage applied to the substrate in a manner to tend to restore the threshold voltage to its desired level.

Abstract translation: 用于以高于电源电压的方式向MOS集成电路的衬底提供负偏压的内部偏置发生器包括泵电路，其包括多个开关，所述多个开关由不重叠的时钟信号依次致动以交替地充电和放电 一个电容器。 时钟信号由发生器产生，该发生器包括耦合到一系列或非门的一系列RC延迟反相放大器级。 偏置发生器还包括阈值敏感调节器，其使用衬底偏置的源体效应对MOS FET的阈值电压来控制所施加的偏置电压的幅度。 当感测到的阈值电压偏离期望的电平时，某些时钟信号被禁用，从而以施加到衬底的偏置电压来修正阈值电压到其期望的电平。

公开(公告)号：US4409499A

公开(公告)日：1983-10-11

申请号：US388160

申请日：1982-06-14

Applicant: John M. Zapisek ,  Gus Giulekas

Inventor： John M. Zapisek ,  Gus Giulekas

IPC: H01L21/82 ,  H01L21/8234 ,  H01L27/088 ,  H03K19/177 ,  G06F7/48 ,  H01L29/78 ,  H03K19/094

CPC classification number: H03K19/17708

Abstract: A programmable logic array includes a plurality of MOS switching devices formed at preselected locations in an array made up of input and output lines and intersecting product term lines. One group of MOS devices constituting the "AND" plane arranged at the intersections of the input lines and product term lines performs a logic operation on input signals to the array and outputs logic signals onto the product term lines. A second group of MOS devices constituting the "OR" plane located at the intersections of the output lines and product term lines receives the outputs of the "AND" plane devices and performs a logic operation on those signals to produce a set of output signals that are presented at the outputs of the array for use by an external device. The merged plane array of the invention advantageously includes dual-gate MOS devices as switching elements to reduce the capacitance on the product term lines and output lines and thereby to increase the operating speed of the array. The input and output lines and related MOS devices of the array rather than being arranged in physically separate and distinct input "AND" and output "OR" planes, as in the prior art, are interspersed or merged with one another so as to reduce the amount of interconnect required between the logic array and an external device which provides the inputs to the array and receives the outputs therefrom.

Abstract translation: 可编程逻辑阵列包括在由输入和输出线构成的阵列中的预选位置处形成的多个MOS开关器件和相交的乘积项线。 布置在输入线和乘积项线的交点处的“AND”平面的一组MOS器件对阵列的输入信号执行逻辑运算，并将逻辑信号输出到乘积项线上。 构成位于输出线和产品项线的交点处的“OR”平面的第二组MOS器件接收“AND”平面器件的输出，并对这些信号执行逻辑运算，以产生一组输出信号， 呈现在阵列的输出端以供外部设备使用。 本发明的合并平面阵列有利地包括作为开关元件的双栅MOS器件，以减少产品项线和输出线上的电容，从而增加阵列的工作速度。 阵列的输入和输出线路和相关的MOS器件不是像现有技术那样布置在物理上分离的和不同的输入“AND”和输出“OR”平面中，而是彼此散布或合并，以便减少 在逻辑阵列和向阵列提供输入并从其接收输出的外部设备之间所需的互连量。

公开(公告)号：US08884589B2

公开(公告)日：2014-11-11

申请号：US13232965

申请日：2011-09-14

Applicant: Timothy J. Knowlton ,  Christopher Fischbach

Inventor： Timothy J. Knowlton ,  Christopher Fischbach

IPC: H02J7/04 ,  H02J7/00

CPC classification number: H02J7/0091 ,  H02J7/0052 ,  H02J2007/0062

Abstract: The invention is related to a method and system for temperature regulation of a power switch during charging of a portable device. The method includes the steps of establishing a connection between the portable device and a charging circuit, monitoring a charging current supplied from the charging circuit to the portable device, monitoring a temperature of the power switch, while the portable device is being charged, comparing the monitored temperature with a predefined threshold temperature, and restricting the charging current, based on the comparison.

Abstract translation: 本发明涉及一种便携式设备充电期间电源开关温度调节的方法和系统。 该方法包括以下步骤：在便携式设备被充电时，建立便携式设备和充电电路之间的连接，监视从充电电路提供给便携式设备的充电电流，监视电源开关的温度， 以预定的阈值温度监测温度，并根据比较来限制充电电流。