公开(公告)号：US20150219721A1

公开(公告)日：2015-08-06

申请号：US14169667

申请日：2014-01-31

Applicant: Analog Devices Technology

Inventor： Hua-Jung Yang ,  Janne Klemetti

IPC: G01R31/36

CPC classification number: G01R31/3651 ,  G01R31/3624 ,  G01R31/3675 ,  H02J7/0016 ,  H02J7/0021 ,  H02J7/0031 ,  H02J7/0036 ,  H02J7/0073

Abstract: A device to determine a state of a battery is disclosed. One or more transistors provide a resistance between first and second nodes. The one or more transistors are configured to conduct a supply current from a battery between the first node and the second node. A measurement circuit measures the voltage generated between the first node and the second node. The measurement circuit further measures the supply voltage. A calculation circuit generates an estimate of the supply current based on the voltage measured between the first node and the second node and the resistance of the one or more transistors. The calculation circuit generates an estimate of the state of charge of the battery based on the measured supply voltage and the estimate of the supply current.

Abstract translation: 公开了一种确定电池状态的装置。 一个或多个晶体管提供第一和第二节点之间的电阻。 一个或多个晶体管被配置为在第一节点和第二节点之间从电池传导供电电流。 测量电路测量在第一节点和第二节点之间产生的电压。 测量电路进一步测量电源电压。 计算电路基于在第一节点和第二节点之间测量的电压和一个或多个晶体管的电阻来产生供电电流的估计。 计算电路基于所测量的电源电压和电源电流的估计，产生电池的充电状态的估计。

公开(公告)号：US09092429B2

公开(公告)日：2015-07-28

申请号：US14040367

申请日：2013-09-27

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Michael S. Allen ,  John L. Redford

IPC: G06F3/06 ,  G06F13/28 ,  G06F13/38

CPC classification number: G06F13/28

Abstract: According to one example embodiment, a direct memory access (DMA) engine and buffer is disclosed. The vector buffer may be explicitly programmable, and may include advanced logic for reordering non-unity-stride vector data. An example MEMCPY instruction may provide an access request to the DMA buffer, which may then service the request asynchronously. Bitwise guards are set over memory in use, and cleared as each bit is read.

Abstract translation: 根据一个示例实施例，公开了直接存储器存取（DMA）引擎和缓冲器。 向量缓冲器可以是可显式可编程的，并且可以包括用于重新排序非单位步幅矢量数据的高级逻辑。 示例MEMCPY指令可以向DMA缓冲器提供访问请求，其可以异步地服务请求。 按位保护设置在使用中的内存中，并在读取每个位时清零。

公开(公告)号：US20150180485A1

公开(公告)日：2015-06-25

申请号：US14134767

申请日：2013-12-19

Applicant: Analog Devices Technology

Inventor： Hyman Shanan ,  Michael F. Keaveney

IPC: H03L7/099 ,  H03L7/093

CPC classification number: H03L7/099 ,  H03L1/026 ,  H03L7/104

Abstract: Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO having a tuning voltage input and a frequency tuning circuit configured to set a frequency band setting of the VCO. The frequency tuning circuit can include a voltage monitor configured to compare the voltage level of the tuning voltage input to one or more tuning voltage threshold levels, a control circuit configured to control at least a frequency band setting and a bias current setting of the VCO, and an amplitude detection circuit configured to compare an amplitude of an oscillation signal of the VCO to one or more amplitude threshold levels.

Abstract translation: 提供了锁相环（PLL）的频率锁定增强的装置和方法。 在一个方面，PLL可以包括具有调谐电压输入的VCO和被配置为设置VCO的频带设置的频率调谐电路。 频率调谐电路可以包括电压监视器，其被配置为将调谐电压输入的电压电平与一个或多个调谐电压阈值电平进行比较，控制电路被配置为至少控制VCO的频带设置和偏置电流设置， 以及振幅检测电路，被配置为将VCO的振荡信号的振幅与一个或多个振幅阈值电平进行比较。

公开(公告)号：US09065479B2

公开(公告)日：2015-06-23

申请号：US14214180

申请日：2014-03-14

Applicant: Analog Devices Technology

Inventor： Dennis A. Dempsey

IPC: H03M1/66 ,  H03M1/68 ,  H03M1/00 ,  H03M1/06 ,  H03M1/76

CPC classification number: H03M1/68 ,  H03M1/00 ,  H03M1/06 ,  H03M1/66 ,  H03M1/682 ,  H03M1/765

Abstract: In an example, a multistring DAC is described and includes at least two DAC stages. Each DAC stage includes a string of impedance elements and a switching network. In one configuration, the multi-string DAC is configured to use the voltage change at terminals of a first string separately to the voltage drop across a first switching network that couples the first and second strings to provide an analog output in response to a digital input to the DAC.

Abstract translation: 在一个示例中，描述了多段DAC并且包括至少两个DAC级。 每个DAC级包括一串阻抗元件和一个交换网络。 在一种配置中，多串DAC被配置为使第一串的端子处的电压变化与跨第一和第二串耦合的第一开关网络的电压降分开，以响应于数字输入而提供模拟输出 到DAC。

公开(公告)号：US20150158114A1

公开(公告)日：2015-06-11

申请号：US14102132

申请日：2013-12-10

Applicant: Analog Devices Technology

Inventor： Bernard Patrick Stenson ,  Paul Martin Lambkin ,  Colette J. Blaney ,  John Beatty

IPC: B23K26/00 ,  H01L27/01

CPC classification number: H01G4/33 ,  H01C7/006 ,  H01C17/242 ,  H01G4/255

Abstract: A phase corrector for laser trimming a component, the phase corrector comprising: a first correction structure located to a first side of the component, the first correction structure comprising first and second correction regions at first and second distances from the component; and a second correction structure located to a second side the component, the second correction structure comprising third and fourth correction regions at third and fourth distances from the component.

Abstract translation: 一种用于激光微调分量的相位校正器，所述相位校正器包括：位于所述分量的第一侧的第一校正结构，所述第一校正结构包括距离所述分量的第一和第二距离处的第一和第二校正区域; 以及位于所述部件的第二侧的第二校正结构，所述第二校正结构包括距所述部件的第三和第四距离处的第三和第四校正区域。

公开(公告)号：US09041363B2

公开(公告)日：2015-05-26

申请号：US13856611

申请日：2013-04-04

Applicant: Analog Devices Technology

Inventor： Hirohisa Tanabe

IPC: G05F1/24 ,  H02M3/158

CPC classification number: H02M3/1582

Abstract: A “windowless” H-bridge buck-boost switching converter includes a regulation circuit with an error amplifier which produces a ‘comp’ signal, a comparison circuit which compares ‘comp’ with a ‘ramp’ signal, and logic circuitry which receives the comparison circuit output and a mode control signal indicating whether the converter is to operate in buck mode or boost mode and operates the primary or secondary switching elements to produce the desired output voltage in buck or boost mode, respectively. A ‘ramp’ signal generation circuit operates to shift the ‘ramp’ signal up by a voltage Vslp(p−p)+Vhys when transitioning from buck to boost mode, and to shift ‘ramp’ back down by Vslp(p−p)+Vhys when transitioning from boost to buck mode, thereby enabling the converter to operate in buck mode or boost mode only, with no need for an intermediate buck-boost region.

Abstract translation: “无窗”H桥降压升压开关转换器包括具有产生“comp”信号的误差放大器的调节电路，将“comp”与“斜坡”信号进行比较的比较电路和接收比较的逻辑电路 电路输出和指示转换器是否以降压模式或升压模式操作的模式控制信号，并分别操作一级或二级开关元件以产生降压或升压模式中的期望输出电压。 “斜坡”信号发生电路在从降压转换到升压模式时将“斜坡”信号向上移动一个电压Vslp（p-p）+ Vhys，并将“斜坡”下移Vslp（p-p） + Vhys从升压转换到降压模式，从而使转换器只能在降压模式或升压模式下工作，无需中间降压 - 升压区域。

公开(公告)号：US20150131705A1

公开(公告)日：2015-05-14

申请号：US14213561

申请日：2014-03-14

Applicant: Analog Devices Technology

Inventor： Haim Primo ,  Yosef Stein ,  Oz Gabai

IPC: H04B1/707

CPC classification number: H04B1/707

Abstract: A modulation scheme for long range transceiver utilizing a processing scheme in combination with a Hadamard transform is disclosed. The processing scheme can correspond to an industry standard or to other processing schemes. An input signal is parallelized through serial to parallel conversion. The processed parallel signals are orthogonalized using a Hadamard transform to allow multiple channel signals with increased throughput. Accordingly, the long range modulation scheme of this invention can achieve high efficiency and increased throughput while meeting performance goals of long range signal transmission.

Abstract translation: 公开了一种使用与Hadamard变换组合的处理方案的长距离收发机的调制方案。 处理方案可以对应于行业标准或其他处理方案。 输入信号通过串行到并行转换并行化。 使用Hadamard变换使处理的并行信号正交化，以允许具有增加的吞吐量的多个信道信号。 因此，本发明的长距离调制方案可以在满足长距离信号传输的性能目标的同时实现高效率和增加的吞吐量。

公开(公告)号：US20150116138A1

公开(公告)日：2015-04-30

申请号：US14065732

申请日：2013-10-29

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Zhao Li ,  David Alldred

IPC: H03M3/00

CPC classification number: H03M3/368 ,  H03M1/00 ,  H03M1/12 ,  H03M3/30 ,  H03M3/38 ,  H03M3/424 ,  H03M3/454

Abstract: An analog-to-digital converter (ADC) can include a continuous-time delta sigma modulator and calibration logic. The calibration logic can calibrate direct feedback and flash clock delay coefficients of the continuous-time delta-sigma modulator without interrupting the normal operations of the ADC (e.g., in situ). Thus, the calibration logic can rectify performance and stability degradation by calibrating suboptimal coefficients.

Abstract translation: 模数转换器（ADC）可以包括连续时间ΔΣ调制器和校准逻辑。 校准逻辑可以校准连续时间Δ-Σ调制器的直接反馈和闪速时钟延迟系数，而不中断ADC的正常操作（例如，原位）。 因此，校准逻辑可以通过校准次优系数来纠正性能和稳定性降级。

公开(公告)号：US20150102391A1

公开(公告)日：2015-04-16

申请号：US14055738

申请日：2013-10-16

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Edward John Coyne

IPC: H01L29/808 ,  H01L29/66

CPC classification number: H01L29/808 ,  H01L29/0843 ,  H01L29/1058 ,  H01L29/66893 ,  H01L29/66901

Abstract: A method of forming a junction field effect transistor, the transistor comprising: a back gate; a channel; a top gate; a drain and a source in current flow with the channel; wherein the method comprises selecting a first channel dimension between the top gate and the back gate such that a significant current flow path in the channel occurs in a region of relatively low electric field strength.

Abstract translation: 一种形成结型场效应晶体管的方法，所述晶体管包括：背栅极; 一个渠道 顶门 电流与通道的漏极和源极; 其中所述方法包括选择所述顶栅极和所述后栅极之间的第一沟道尺寸，使得所述沟道中的有效电流流动路径发生在相对低的电场强度的区域中。

公开(公告)号：US20150073739A1

公开(公告)日：2015-03-12

申请号：US14020404

申请日：2013-09-06

Applicant: Analog Devices Technology

Inventor： Muhammad Kalimuddin Khan ,  Kenneth J. Mulvaney ,  Michale Deeney ,  Niall Kevin Kearney

IPC: G01R23/02

CPC classification number: G01R23/02 ,  H03L7/095 ,  H03L7/193 ,  H03L7/1974 ,  H03L7/1976

Abstract: A monitoring circuit for monitoring the performance of a phase locked loop having a divider therein, the divider comprising at least a first counter, the monitoring circuit comprising at least one memory element for capturing a value of the first counter after a predetermined time from a system event in the operation of the phase locked loop, a variability calculator for comparing a value of the counter with a preceding value of the counter to calculate a variation, and a circuit responsive to the estimate of variation for outputting a status signal.

Abstract translation: 一种用于监视其中具有分频器的锁相环的性能的监视电路，所述分频器包括至少第一计数器，所述分频器包括至少一个存储器元件，用于在来自系统的预定时间之后捕获所述第一计数器的值 可变性计算器，用于将计数器的值与计数器的先前值进行比较以计算变化;以及电路，其响应于用于输出状态信号的变化估计。