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    Method for Fabricating Semiconductor Device
    61.
    发明申请
    Method for Fabricating Semiconductor Device 审中-公开
    半导体器件制造方法

    公开(公告)号：US20110306208A1

    公开(公告)日：2011-12-15

    申请号：US13157393

    申请日：2011-06-10

    申请人： Jung-Won Lee ,  Dae-Hyuk Kang ,  Bo-Un Yoon ,  Kun-Tack Lee

    发明人： Jung-Won Lee ,  Dae-Hyuk Kang ,  Bo-Un Yoon ,  Kun-Tack Lee

    IPC分类号： H01L21/28

    CPC分类号： H01L28/91

    摘要： Methods for forming a mold for a storage electrode in a semiconductor device include forming an interlayer dielectric layer including a contact plug on a substrate. A first mold dielectric layer is formed of a first material on the interlayer dielectric layer. A second mold dielectric layer is formed of a second material on the first mold dielectric layer. The second material has a different etch selectivity than the first material. A first opening is formed that penetrates the first and second mold dielectric layers. The first opening is dry etched to define a second opening having a larger width in the first mold dielectric layer than in the second mold dielectric layer based on the different etch selectivity of the first and second mold dielectric layers to define the mold for the storage electrode.

    摘要翻译： 在半导体器件中形成用于存储电极的模具的方法包括在衬底上形成包括接触插塞的层间介电层。 第一模具电介质层由层间电介质层上的第一材料形成。 第二模具电介质层由第一模具电介质层上的第二材料形成。 第二种材料具有与第一种材料不同的蚀刻选择性。 形成穿过第一和第二模具电介质层的第一开口。 基于第一和第二模具电介质层的不同蚀刻选择性来限定用于存储电极的模具，第一开口被干蚀刻以限定在第一模具电介质层中具有比在第二模具电介质层中更大的宽度的第二开口 。

    METHODS OF FORMING AN ISOLATION LAYER AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING AN ISOLATION LAYER
    62.
    发明申请
    METHODS OF FORMING AN ISOLATION LAYER AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING AN ISOLATION LAYER 失效
    形成隔离层的方法和制造具有隔离层的半导体器件的方法

    公开(公告)号：US20110281415A1

    公开(公告)日：2011-11-17

    申请号：US13109527

    申请日：2011-05-17

    申请人： Dae-Hyuk KANG ,  Jung-Won Lee ,  Bo-Un Yoon ,  Kun-Tack Lee

    发明人： Dae-Hyuk KANG ,  Jung-Won Lee ,  Bo-Un Yoon ,  Kun-Tack Lee

    IPC分类号： H01L21/31

    CPC分类号： H01L21/76229 ,  H01L21/28273 ,  H01L27/11526 ,  H01L27/11531

    摘要： In a method of forming an isolation layer, first and second trenches are formed on a substrate. The first and the second trenches have first and second widths, respectively, and the second width is greater than the first width. A second isolation layer pattern partially fills the second trench. A first isolation layer pattern and the third isolation layer pattern are formed. The first isolation layer pattern fills the first trench, and the third isolation layer pattern is formed on the second isolation layer pattern and fills a remaining portion of the second trench.

    摘要翻译： 在形成隔离层的方法中，在衬底上形成第一和第二沟槽。 第一和第二沟槽分别具有第一宽度和第二宽度，第二宽度大于第一宽度。 第二隔离层图案部分地填充第二沟槽。 形成第一隔离层图案和第三隔离层图案。 第一隔离层图案填充第一沟槽，并且第三隔离层图案形成在第二隔离层图案上并且填充第二沟槽的剩余部分。

    Apparatus for polishing a wafer and method for detecting a polishing end point by the same
    64.
    发明授权
    Apparatus for polishing a wafer and method for detecting a polishing end point by the same 有权
    用于抛光晶片的装置和用于检测抛光终点的方法

    公开(公告)号：US08038508B2

    公开(公告)日：2011-10-18

    申请号：US12285852

    申请日：2008-10-15

    申请人： Jong-Heun Lim ,  Sung-Ho Shin ,  Bo-Un Yoon ,  Chang-Ki Hong

    发明人： Jong-Heun Lim ,  Sung-Ho Shin ,  Bo-Un Yoon ,  Chang-Ki Hong

    IPC分类号： B24B49/00

    CPC分类号： B24B9/065 ,  B24B21/02 ,  B24B37/013 ,  B24B49/12

    摘要： A wafer polishing apparatus includes a polishing tape extending between two guide rollers, a first surface of the polishing tape contacting a surface of a wafer to be polished, a polishing head including a pusher pad, the pusher pad adapted to push the polishing tape against the surface of the wafer to be polished, a color image sensor adjacent to the polishing tape, the color image sensor being adapted to detect a color image of the polishing tape and to output a signal corresponding to the detected color image, and a controller connected to the color image sensor, the controller being adapted to receive the signal output from the color image sensor and to determine when a color of the color image detected by the color image sensor changes, a change in the color image indicating a polishing end point.

    摘要翻译： 晶片抛光装置包括在两个导辊之间延伸的研磨带，抛光带的与待抛光晶片的表面接触的第一表面，包括推动垫的抛光头，该推动垫适于将抛光带推向 要抛光的晶片的表面，邻近抛光带的彩色图像传感器，彩色图像传感器适于检测研磨带的彩色图像并输出与检测到的彩色图像相对应的信号，以及控制器，连接到 所述彩色图像传感器，所述控制器适于接收从彩色图像传感器输出的信号，并且确定由彩色图像传感器检测到的彩色图像的颜色何时改变指示抛光终点的彩色图像的变化。

    Method of fabricating non-volatile memory integrated circuit device and non-volatile memory integrated circuit device fabricated using the same
    65.
    发明授权
    Method of fabricating non-volatile memory integrated circuit device and non-volatile memory integrated circuit device fabricated using the same 有权
    制造非易失性存储器集成电路器件的方法和使用其制造的非易失性存储器集成电路器件

    公开(公告)号：US08030150B2

    公开(公告)日：2011-10-04

    申请号：US12397543

    申请日：2009-03-04

    申请人： Byoung-ho Kwon ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

    发明人： Byoung-ho Kwon ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

    摘要： A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.

    摘要翻译： 提供了一种制造使用该方法制造的非易失性存储器集成电路器件和非易失性存储器集成电路器件的方法。 器件隔离区域形成在衬底中以限定电池阵列区域和外围电路区域。 在单元阵列区域中形成多个第一和第二预叠层栅极结构，并且每个都具有堆叠下部结构，导电图案和第一牺牲层图案的结构。 结区域形成在单元阵列区域中。 间隔件形成在第一和第二预堆叠栅极结构的侧壁上。 形成填充第二预堆叠栅极结构之间的每个空间的第二牺牲层图案。 第一牺牲层图案从第一和第二预堆叠栅极结构中的每一个去除。 在第一和第二预堆叠栅极结构的每个空间中形成镶嵌金属层图案，从中去除第一牺牲层图案，从而完成第一和第二堆叠栅极结构。 去除第二牺牲层图案。 在第一层叠栅极结构的顶表面，第二堆叠栅结构的顶表面和侧壁以及衬底的顶表面上形成停止层。

    LOW-RESISTANCE CONDUCTIVE PATTERN STRUCTURES AND METHODS OF FABRICATING THE SAME
    67.
    发明申请
    LOW-RESISTANCE CONDUCTIVE PATTERN STRUCTURES AND METHODS OF FABRICATING THE SAME 有权
    低电阻导电图案结构及其制作方法

    公开(公告)号：US20110100693A1

    公开(公告)日：2011-05-05

    申请号：US12910356

    申请日：2010-10-22

    申请人： Byoung-Ho Kwon ,  Bo-Un Yoon

    发明人： Byoung-Ho Kwon ,  Bo-Un Yoon

    IPC分类号： H05K1/18 ,  H05K1/02

    CPC分类号： H01L23/528 ,  H01L21/76807 ,  H01L21/76816 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A conductive structure includes a contact plug extending through an insulating layer on a substrate, and first and second conductive lines extending alongside one another on the insulating layer. The first conductive line extends on the contact plug. A connecting line on the insulating layer extends between and electrically connects the first and second conductive lines. Related integrated circuit devices and fabrication methods are also discussed.

    摘要翻译： 导电结构包括延伸穿过衬底上的绝缘层的接触插塞以及在绝缘层上彼此并排延伸的第一和第二导电线。 第一导线延伸在接触插头上。 绝缘层上的连接线在第一和第二导电线之间延伸并电连接。 还讨论了相关的集成电路器件和制造方法。

    VERTICAL-TYPE SEMICONDUCTOR DEVICE
    68.
    发明申请
    VERTICAL-TYPE SEMICONDUCTOR DEVICE 有权
    垂直型半导体器件

    公开(公告)号：US20110073866A1

    公开(公告)日：2011-03-31

    申请号：US12872270

    申请日：2010-08-31

    申请人： Young-Hoo Kim ,  Hyo-San Lee ,  Sang-Won Bae ,  Bo-Un Yoon ,  Kun-Tack Lee

    发明人： Young-Hoo Kim ,  Hyo-San Lee ,  Sang-Won Bae ,  Bo-Un Yoon ,  Kun-Tack Lee

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11578 ,  H01L27/11556 ,  H01L27/11582

    摘要： In a vertical-type non-volatile memory device, an insulation layer pattern is provided on a substrate, the insulation layer pattern having a linear shape. Single-crystalline semiconductor patterns are provided on the substrate to make contact with both sidewalls of the insulation layer pattern, the single-crystalline semiconductor patterns having a pillar shape that extends in a vertical direction relative to the substrate. A tunnel oxide layer is provided on the single-crystalline semiconductor pattern. A lower electrode layer pattern is provided on the tunnel oxide layer and on the substrate. A plurality of insulation interlayer patterns is provided on the lower electrode layer pattern, the insulation interlayer patterns being spaced apart from one another by a predetermined distance along the single-crystalline semiconductor pattern. A charge-trapping layer and a blocking dielectric layer are sequentially formed on the tunnel oxide layer between the insulation interlayer patterns. A plurality of control gate patterns is provided on the blocking dielectric layer between the insulation interlayer patterns. An upper electrode layer pattern is provided on the tunnel oxide layer and on the uppermost insulation interlayer pattern.

    摘要翻译： 在垂直型非易失性存储器件中，在衬底上设置绝缘层图案，绝缘层图案具有直线形状。 单晶半导体图案设置在基板上以与绝缘层图案的两个侧壁接触，单晶半导体图案具有相对于基板在垂直方向上延伸的柱状。 隧道氧化物层设置在单晶半导体图案上。 在隧道氧化物层和衬底上设置下电极层图案。 在下电极层图案上设置多个绝缘层间图案，绝缘层间图案沿着单晶半导体图案彼此隔开预定距离。 在绝缘层间图案之间的隧道氧化物层上依次形成电荷捕获层和阻挡介质层。 在绝缘夹层图案之间的阻挡介质层上设置多个控制栅极图案。 在隧道氧化物层和最上层的绝缘层间图案上设置上电极层图案。

    Polishing Pads Including Sidewalls and Related Polishing Apparatuses
    69.
    发明申请
    Polishing Pads Including Sidewalls and Related Polishing Apparatuses 失效
    抛光垫包括侧壁和相关的抛光设备

    公开(公告)号：US20110039480A1

    公开(公告)日：2011-02-17

    申请号：US12855164

    申请日：2010-08-12

    申请人： Jae-Kwang Choi ,  Bo-Un Yoon ,  Myung-Ki Hong

    发明人： Jae-Kwang Choi ,  Bo-Un Yoon ,  Myung-Ki Hong

    IPC分类号： B24B7/00 ,  B24D11/00

    CPC分类号： B24B21/004 ,  B24B37/245 ,  B24B37/26

    摘要： A polishing pad may include a base and a plurality of polishing protrusions on a surface of the base. Each polishing protrusion may include a sidewall defining an opening in a surface of the polishing protrusion opposite the base. In addition, portions of the sidewall opposite the base may define a contact surface.

    摘要翻译： 抛光垫可以包括基底和在基底的表面上的多个抛光突起。 每个抛光突起可以包括限定在与基座相对的抛光突起的表面中的开口的侧壁。 此外，与基座相对的侧壁的部分可以限定接触表面。