公开(公告)号：US20110316168A1

公开(公告)日：2011-12-29

申请号：US12913748

申请日：2010-10-27

申请人： Kwang-Jin Moon ,  Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Dong-Chan Lim ,  Deok-Young Jung

发明人： Kwang-Jin Moon ,  Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Dong-Chan Lim ,  Deok-Young Jung

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/528 ,  H01L2224/16146 ,  H01L2225/06541 ,  H01L2924/01327 ,  H01L2924/00

摘要： A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure.

摘要翻译： 半导体器件包括通孔结构和导电结构。 通孔结构具有平坦部分和突出部分的表面。 导电结构形成在平面部分的至少一部分上，而不是在通孔结构的突出部分的至少一部分之上。 例如，导电结构仅形成在平面部分上，而不形成在任何突出部分上，用于在导电结构和通孔结构之间形成高质量的连接。

公开(公告)号：US07737038B2

公开(公告)日：2010-06-15

申请号：US11567927

申请日：2006-12-07

申请人： Seung-Mahn Lee ,  Byung-Lyul Park ,  MooJin Jung

发明人： Seung-Mahn Lee ,  Byung-Lyul Park ,  MooJin Jung

IPC分类号： H01L21/302

CPC分类号： H01L21/3212 ,  B24B37/013 ,  B24B49/105 ,  H01L22/26 ,  H01L2924/0002 ,  Y10S438/959 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device includes forming a conductive layer on an insulating layer having a plurality of trenches on a semiconductor substrate, such that the conductive layer fills in the plurality of trenches formed in the insulating layer, and calculating a target eddy current value to measure an end point using parameters of a pattern density and a depth of the trenches. The method further includes planarizing the conductive layer and measuring eddy current values on the conductive layer using an eddy current monitoring system, and stopping the planarization when the measured eddy current value reaches the target eddy current value to form a planarized conductive layer having a target height on the insulating layer.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上在具有多个沟槽的绝缘层上形成导电层，使得导电层填充在绝缘层中形成的多个沟槽中，并计算目标涡流值 使用模式密度和沟槽深度的参数来测量终点。 该方法还包括使用涡流监测系统平坦化导电层并测量导电层上的涡流值，并且当测量的涡流值达到目标涡流值时停止平坦化，以形成具有目标高度的平坦化导电层 在绝缘层上。

公开(公告)号：US07348277B2

公开(公告)日：2008-03-25

申请号：US11352640

申请日：2006-02-13

申请人： Ja-Eung Koo ,  Byung-Lyul Park

发明人： Ja-Eung Koo ,  Byung-Lyul Park

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/7688 ,  H01L21/76819

摘要： There are provided methods of fabricating a semiconductor device using a sacrificial layer. The methods provide an approach to maintaining thickness distribution of the interlayer insulating layers below a sacrificial layer uniform on an overall surface of a semiconductor substrate during performing a chemical mechanical polishing (CMP) process in a damascene process. To this end, the method includes forming a pad layer, a pad interlayer insulating layer, an etch stop layer pattern, a planarized interlayer insulating layer and a sacrificial layer sequentially on a semiconductor substrate. At least one trench is formed in the sacrificial layer and the planarized interlayer insulating layer. A via contact hole is formed in the etch stop layer pattern, the pad interlayer insulating layer, and the pad layer to be disposed below the trench. A diffusion barrier layer and a conductive layer are sequentially formed to fill the trench and the via contact hole. A CMP process is performed on the conductive layer, the diffusion barrier layer, and the sacrificial layer.

摘要翻译： 提供了使用牺牲层制造半导体器件的方法。 这些方法提供了一种在大理石工艺中进行化学机械抛光（CMP）工艺期间，在半导体衬底的整个表面上均匀地保持牺牲层的厚度分布的方法。 为此，该方法包括在半导体衬底上依次形成焊盘层，焊盘层间绝缘层，蚀刻停止层图案，平坦化的层间绝缘层和牺牲层。 在牺牲层和平坦化层间绝缘层中形成至少一个沟槽。 在蚀刻停止层图案，焊盘层间绝缘层和焊盘层中形成通孔接触孔，以设置在沟槽下方。 依次形成扩散阻挡层和导电层以填充沟槽和通孔接触孔。 在导电层，扩散阻挡层和牺牲层上执行CMP工艺。

公开(公告)号：US20070196994A1

公开(公告)日：2007-08-23

申请号：US11567927

申请日：2006-12-07

申请人： Seung-Mahn Lee ,  Byung-Lyul Park ,  MooJin Jung

发明人： Seung-Mahn Lee ,  Byung-Lyul Park ,  MooJin Jung

IPC分类号： H01L21/20

CPC分类号： H01L21/3212 ,  B24B37/013 ,  B24B49/105 ,  H01L22/26 ,  H01L2924/0002 ,  Y10S438/959 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device includes forming a conductive layer on an insulating layer having a plurality of trenches on a semiconductor substrate, such that the conductive layer fills in the plurality of trenches formed in the insulating layer, and calculating a target eddy current value to measure an end point using parameters of a pattern density and a depth of the trenches. The method further includes planarizing the conductive layer and measuring eddy current values on the conductive layer using an eddy current monitoring system, and stopping the planarization when the measured eddy current value reaches the target eddy current value to form a planarized conductive layer having a target height on the insulating layer.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上在具有多个沟槽的绝缘层上形成导电层，使得导电层填充在绝缘层中形成的多个沟槽中，并计算目标涡流值 使用模式密度和沟槽深度的参数来测量终点。 该方法还包括使用涡流监测系统平坦化导电层并测量导电层上的涡流值，并且当测量的涡流值达到目标涡流值时停止平坦化，以形成具有目标高度的平坦化导电层 在绝缘层上。

公开(公告)号：US20060183333A1

公开(公告)日：2006-08-17

申请号：US11352640

申请日：2006-02-13

申请人： Ja-Eung Koo ,  Byung-Lyul Park

发明人： Ja-Eung Koo ,  Byung-Lyul Park

IPC分类号： H01L21/461 ,  C23F1/00 ,  B44C1/22

CPC分类号： H01L21/7688 ,  H01L21/76819

摘要： There are provided methods of fabricating a semiconductor device using a sacrificial layer. The methods provide an approach to maintaining thickness distribution of the interlayer insulating layers below a sacrificial layer uniform on an overall surface of a semiconductor substrate during performing a chemical mechanical polishing (CMP) process in a damascene process. To this end, the method includes forming a pad layer, a pad interlayer insulating layer, an etch stop layer pattern, a planarized interlayer insulating layer and a sacrificial layer sequentially on a semiconductor substrate. At least one trench is formed in the sacrificial layer and the planarized interlayer insulating layer. A via contact hole is formed in the etch stop layer pattern, the pad interlayer insulating layer, and the pad layer to be disposed below the trench. A diffusion barrier layer and a conductive layer are sequentially formed to fill the trench and the via contact hole. A CMP process is performed on the conductive layer, the diffusion barrier layer, and the sacrificial layer.

摘要翻译： 提供了使用牺牲层制造半导体器件的方法。 这些方法提供了一种在大理石过程中执行化学机械抛光（CMP）工艺期间，在半导体衬底的整个表面上均匀地保持牺牲层的厚度分布的方法。 为此，该方法包括在半导体衬底上依次形成焊盘层，焊盘层间绝缘层，蚀刻停止层图案，平坦化的层间绝缘层和牺牲层。 在牺牲层和平坦化层间绝缘层中形成至少一个沟槽。 在蚀刻停止层图案，焊盘层间绝缘层和焊盘层中形成通孔接触孔，以设置在沟槽下方。 依次形成扩散阻挡层和导电层以填充沟槽和通孔接触孔。 在导电层，扩散阻挡层和牺牲层上执行CMP工艺。

公开(公告)号：US6087257A

公开(公告)日：2000-07-11

申请号：US751153

申请日：1996-11-15

申请人： Byung-lyul Park ,  Jung-min Ha ,  Dae-hong Ko ,  Sang-in Lee

发明人： Byung-lyul Park ,  Jung-min Ha ,  Dae-hong Ko ,  Sang-in Lee

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76855 ,  H01L21/76843 ,  H01L21/76879

摘要： Methods for fabricating a tungsten nitride layer in a semiconductor substrate having an insulating layer formed thereon. The methods include forming a contact hole through the insulating layer. A tungsten nitride layer is then selectively deposited only in the contact hole by selectively reacting a nitrogen-containing gas with a tungsten source gas so as to prevent formation of tungsten nitride layer on the insulating layer outside the contact hole. Methods or fabricating metal wiring utilizing the methods of fabricating a tungsten nitride layer are also provided.

摘要翻译： 在其上形成有绝缘层的半导体衬底中制造氮化钨层的方法。 所述方法包括形成穿过绝缘层的接触孔。 然后通过选择性地使含氮气体与钨源气体反应来选择性地沉积氮化钨层，以防止在接触孔外部的绝缘层上形成氮化钨层。 还提供了利用制造氮化钨层的方法或制造金属布线的方法。

公开(公告)号：US09847276B2

公开(公告)日：2017-12-19

申请号：US14463645

申请日：2014-08-19

申请人： Pil-Kyu Kang ,  Byung Lyul Park ,  SungHee Kang ,  Taeseong Kim ,  Taeyeong Kim ,  Kwangjin Moon ,  Jae-Hwa Park ,  Sukchul Bang ,  Seongmin Son ,  Jin Ho An ,  Ho-Jin Lee ,  Jeonggi Jin

发明人： Pil-Kyu Kang ,  Byung Lyul Park ,  SungHee Kang ,  Taeseong Kim ,  Taeyeong Kim ,  Kwangjin Moon ,  Jae-Hwa Park ,  Sukchul Bang ,  Seongmin Son ,  Jin Ho An ,  Ho-Jin Lee ,  Jeonggi Jin

IPC分类号： H01L29/40 ,  H01L23/48 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer.

公开(公告)号：US09679829B2

公开(公告)日：2017-06-13

申请号：US14809159

申请日：2015-07-24

申请人： Kwangjin Moon ,  SungHee Kang ,  Taeseong Kim ,  Byung Lyul Park ,  Yeun-Sang Park ,  Sukchul Bang

发明人： Kwangjin Moon ,  SungHee Kang ,  Taeseong Kim ,  Byung Lyul Park ,  Yeun-Sang Park ,  Sukchul Bang

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L21/306 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/481 ,  H01L21/30625 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/53238 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2224/05552

摘要： Provided are semiconductor devices and methods of fabricating the same. The device may include a substrate including a first surface and a second surface opposing each other, a through-silicon-via (TSV) electrode provided in a via hole that may be formed to penetrate the substrate, and an integrated circuit provided adjacent to the through electrode on the first surface. The through electrode includes a metal layer filling a portion of the via hole and an alloy layer filling a remaining portion of the via hole. The alloy layer contains at least two metallic elements, one of which may be the same as that contained in the metal layer, and the other of which may be different from that contained in the metal layer.

公开(公告)号：US09673133B2

公开(公告)日：2017-06-06

申请号：US14939394

申请日：2015-11-12

申请人： Jae-Hwa Park ,  Kwangjin Moon ,  Byung Lyul Park ,  Sukchul Bang

发明人： Jae-Hwa Park ,  Kwangjin Moon ,  Byung Lyul Park ,  Sukchul Bang

IPC分类号： H01L23/48 ,  H01L23/50 ,  H01L23/528

CPC分类号： H01L23/481 ,  H01L23/50 ,  H01L23/528 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices having through-electrodes are provided. The semiconductor devices may include a substrate, a through-electrode penetrating vertically through the substrate, a circuit layer on the substrate and metal lines in the circuit layer. The metal lines may include two first metals on opposing edges of a top surface of the through-electrode and second metals above the top surface of the through-electrode. At least some of the second metals may not vertically overlap the two first metals.

公开(公告)号：US20160268182A1

公开(公告)日：2016-09-15

申请号：US15065903

申请日：2016-03-10

申请人： HO-JIN LEE ,  BYUNG LYUL PARK ,  JIN HO AN

发明人： HO-JIN LEE ,  BYUNG LYUL PARK ,  JIN HO AN

IPC分类号： H01L23/48 ,  H01L23/532 ,  H01L23/528

CPC分类号： H01L23/481 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/53238 ,  H01L23/5384 ,  H01L23/5385 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

摘要： A semiconductor device includes a semiconductor substrate, a circuit layer including an interlayer insulating layer on an upper surface of the substrate, and a conductive via penetrating through the interlayer insulating layer and the substrate, and electrically connected to the circuit layer. The device further includes an insulating layer surrounding the conductive via, and located between the conductive via and the substrate and between the conductive via and interlayer insulating layer, and a buffer layer located between the insulating layer and the conductive via, and overlapping at least a portion of the interlayer insulating layer in a depth direction of the conductive via.

摘要翻译： 半导体器件包括半导体衬底，在衬底的上表面上包括层间绝缘层的电路层和穿过层间绝缘层和衬底的导电通孔，并电连接到电路层。 该器件还包括围绕导电通孔的绝缘层，并且位于导电通孔和衬底之间以及导电通孔和层间绝缘层之间，以及位于绝缘层和导电通孔之间的缓冲层，并且至少与 层间绝缘层的一部分在导电通孔的深度方向上。