公开(公告)号：US20120153434A1

公开(公告)日：2012-06-21

申请号：US12969004

申请日：2010-12-15

Applicant: Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  Anthony K. Stamper

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  Anthony K. Stamper

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L28/82 ,  H01L23/5223 ,  H01L27/0207 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metal-insulator-metal (MIM) capacitors and methods for fabricating MIM capacitors. The MIM capacitor includes an interlayer dielectric (ILD) layer with apertures each bounded by a plurality of sidewalls and each extending from the top surface of the ILD layer into the first interlayer dielectric layer. A layer stack, which is disposed on the sidewalls of the apertures and the top surface of the ILD layer, includes a bottom conductive electrode, a top conductive electrode, and a capacitor dielectric between the bottom and top conductive electrodes.

Abstract translation: 金属绝缘体金属（MIM）电容器和制造MIM电容器的方法。 MIM电容器包括层间绝缘层（ILD）层，其中各孔由多个侧壁限定，并且各自从ILD层的顶表面延伸到第一层间电介质层。 布置在孔的侧壁和ILD层的顶表面上的层叠层包括底部导电电极，顶部导电电极和位于底部和顶部导电电极之间的电容器电介质。

公开(公告)号：US08010927B2

公开(公告)日：2011-08-30

申请号：US12127245

申请日：2008-05-27

Applicant: Robert J. Gauthier, Jr. ,  Junjun Li

Inventor： Robert J. Gauthier, Jr. ,  Junjun Li

IPC: G06F17/50 ,  G06F9/45 ,  G06F9/455 ,  H01L23/53 ,  H01L23/62 ,  H01L29/66

CPC classification number: G06F17/5045 ,  H01L27/0285 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Design structure for an electrostatic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The design structure for the ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs, and a trigger for triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.

Abstract translation: 用于保护集成电路芯片免受ESD事件的静电放电（ESD）保护电路的设计结构。 ESD保护电路的设计结构包括一堆BigFET，用于驱动BigFET栅极的BigFET栅极驱动器，以及用于触发BigFET栅极驱动器以响应于ESD事件来驱动BigFET栅极的触发器。 BigFET栅极驱动器包括用于拉低下一个BigFET的栅极的栅极上拉电路。 栅极上拉电路被配置为消除对堆叠的BigFET之间的扩散接触的需要，导致实现ESD保护电路所需的芯片面积的显着节省。

公开(公告)号：US07943438B2

公开(公告)日：2011-05-17

申请号：US12031084

申请日：2008-02-14

Applicant: Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra

Inventor： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra

IPC: H01L21/332

CPC classification number: H01L29/7436 ,  H01L27/0259 ,  H01L29/861

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated.

Abstract translation: 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括一个P + -N体二极管和一个N + -P体二极管。 P + -N体二极管和N + -P体二极管横向集成。

公开(公告)号：US20110049683A1

公开(公告)日：2011-03-03

申请号：US12553523

申请日：2009-09-03

Applicant: Michel J. Abou-Khalil ,  Robert J. GAUTHIER, JR. ,  Tom C. LEE ,  Junjun LI ,  Souvick MITRA ,  Christopher S. PUTNAM ,  Robert R. ROBISON

Inventor： Michel J. Abou-Khalil ,  Robert J. GAUTHIER, JR. ,  Tom C. LEE ,  Junjun LI ,  Souvick MITRA ,  Christopher S. PUTNAM ,  Robert R. ROBISON

IPC: H01L29/861 ,  H01L21/265 ,  H01L21/30

CPC classification number: H01L21/324 ,  H01L27/0255 ,  H01L29/8611 ,  H01L29/866

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract translation: 为纳秒电脉冲退火工艺提供了结构和方法。 形成静电放电（ESD）N + / P +结构的方法包括在衬底上形成N +扩散和在衬底上形成P +扩散。 P +扩散与N +扩散电接触。 该方法还包括在N +扩散和P +扩散之间形成器件。 退火结构或材料的方法包括跨多个纳秒的静电放电（ESD）N + / P +结构施加电脉冲。

公开(公告)号：US07881028B2

公开(公告)日：2011-02-01

申请号：US12041962

申请日：2008-03-04

Applicant: Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC: H02H9/00

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device and/or circuit having an e-fuse is provided to disable a triggering network, and more specifically, an e-fuse is used to disable an electrostatic discharge (ESD) RC triggering network after device installation. The device and/or circuit includes a triggering network electrically coupled to an electrostatic discharge (ESD) protection device. An e-fuse is electrically coupled with the triggering network and configured to render the ESD protection device insensitive to a triggering signal after blowing the e-fuse.

Abstract translation: 提供具有电子保险丝的装置和/或电路以禁用触发网络，更具体地，使用电子熔丝来在设备安装之后禁用静电放电（ESD）RC触发网络。 该装置和/或电路包括电耦合到静电放电（ESD）保护装置的触发网络。 电子熔丝与触发网络电耦合并且被配置为使得ESD保护装置在吹动电熔丝之后对触发信号不敏感。

公开(公告)号：US20110001551A1

公开(公告)日：2011-01-06

申请号：US12496002

申请日：2009-07-01

Applicant: Michel J. Abou-Khalil ,  Tom C. Lee ,  Junjun Li ,  Robert J. Gauthier, JR. ,  Christopher S. Putnam ,  Souvick Mitra

Inventor： Michel J. Abou-Khalil ,  Tom C. Lee ,  Junjun Li ,  Robert J. Gauthier, JR. ,  Christopher S. Putnam ,  Souvick Mitra

IPC: H01H37/76

CPC classification number: G11C17/16 ,  G11C11/5692 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/14 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are embodiments of an e-fuse programming/re-programming circuit. In one embodiment, the e-fuse has two short high atomic diffusion resistance conductor layers positioned on opposite sides and at a same end of a long low atomic diffusion resistance conductor layer. A voltage source is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces. The formation of such opens and/or shorts can be used to achieve different programming states. Other circuit structure embodiments incorporate e-fuses with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.

Abstract translation: 公开了电子熔丝编程/重新编程电路的实施例。 在一个实施例中，电熔丝具有位于长低的原子扩散电阻较长的导体层的相对侧和同一端的两个短的高原子扩散电阻的导体层。 使用电压源来改变施加到端子的电压的极性和可选的电压的大小，以便控制长导体层内的电子的双向流动，从而在长导体上形成开路和/或短路 层 - 短导体层接口。 可以使用这种打开和/或短路的形成来实现不同的编程状态。 其他电路结构实施例包括具有附加导体层和附加端子的电子保险丝，以便允许甚至更多的编程状态。 还公开了相关联的电熔丝编程和重新编程方法的实施例。

公开(公告)号：US07772651B2

公开(公告)日：2010-08-10

申请号：US12013101

申请日：2008-01-11

Applicant: Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Mitra Souvick

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Mitra Souvick

IPC: H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: High-voltage device structures, methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes, and design structures for high-voltage circuits. The planar device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a semiconductor body positioned between two gate electrodes. The gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrent with a process forming device isolation regions.

Abstract translation: 高电压器件结构，使用互补金属氧化物半导体（CMOS）工艺制造这种器件结构的方法，以及高压电路的设计结构。 使用绝缘体上半导体（SOI）衬底形成的平面器件结构包括位于两个栅电极之间的半导体本体。 栅电极和半导体本体可以由SOI衬底的单晶SOI层形成。 电介质层将每个栅电极与半导体本体分开。 这些电介质层通过在SOI层中限定沟槽并用介电材料填充沟槽而形成，其可以与形成器件隔离区的工艺同时发生。

公开(公告)号：US20100155775A1

公开(公告)日：2010-06-24

申请号：US12342228

申请日：2008-12-23

Applicant: Robert J. GAUTHIER, JR. ,  Junjun LI ,  Ankit SRIVASTAVA

Inventor： Robert J. GAUTHIER, JR. ,  Junjun LI ,  Ankit SRIVASTAVA

IPC: H01L29/73 ,  H01L21/331 ,  G06F17/50

CPC classification number: H01L29/66386 ,  H01L24/06 ,  H01L27/0262 ,  H01L29/74 ,  H01L29/7436 ,  H01L2224/05554 ,  H01L2924/14 ,  H01L2924/00

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes first and second silicon controlled rectifiers (SCRs) formed in a substrate. Further, the first and the second SCRs each include at least one component commonly shared between the first and the second SCRs.

Abstract translation: 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括形成在衬底中的第一和第二可控硅整流器（SCR）。 此外，第一和第二SCR各自包括在第一和第二SCR之间共同共享的至少一个部件。

公开(公告)号：US07646573B2

公开(公告)日：2010-01-12

申请号：US12133424

申请日：2008-06-05

Applicant: Albert M. Chu ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Thomas W. Wyckoff

Inventor： Albert M. Chu ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Thomas W. Wyckoff

IPC: H02H9/00 ,  H02H1/00

CPC classification number: H01L27/0266

Abstract: An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) includes an RC trigger device configured between a pair of power rails, a first control path coupled to the RC trigger device, and a second control path coupled to the RC trigger device. A power clamp is configured between the power rails for discharging current from an ESD event, the power clamp having an input coupled to outputs of the first and second control paths, the power clamp independently controllable by the first and second control paths. The first and second control paths are further configured to prevent the power clamp from reactivating following an initial deactivation of the power clamp.

Abstract translation: 用于保护集成电路免受静电放电（ESD）的装置包括RC触发装置，其配置在耦合到RC触发装置的一对电源轨，第一控制路径和耦合到RC触发装置的第二控制路径之间。 功率钳被配置在用于从ESD事件放电的电源轨之间，功率钳具有耦合到第一和第二控制路径的输出的输入，功率钳由第一和第二控制路径独立地控制。 第一和第二控制路径还被配置为防止在电源钳的初始去激活之后电源钳位被重新激活。

公开(公告)号：US20080145958A1

公开(公告)日：2008-06-19

申请号：US11611258

申请日：2006-12-15

Applicant: Michel J. Abou-Khalil ,  Robert J. Gauthier ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher Stephen Putnam

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher Stephen Putnam

IPC: H01L21/66 ,  H01L23/58

CPC classification number: H01L22/14 ,  H01L22/20 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A monitor semiconductor chip that incorporates ESD sensitive resistors is subjected to the same steps in a semiconductor manufacturing process to which functional semiconductor chips are subjected. The ESD sensitive resistors are configured to experience non-volatile changes in resistance in response to ESD events, such that the resistors retain the changes in resistance after dissipation of the ESD events have occurred. As a result, the occurrence of an ESD event, and in some instances, the magnitude of an ESD event, can be detected by monitoring the resistance of the ESD sensitive resistors after one or more steps in a semiconductor manufacturing process.

Abstract translation: 在ESD功能半导体芯片受到的半导体制造工序中，具有ESD敏感电阻的监视器半导体芯片进行相同的工序。 ESD敏感电阻被配置为响应于ESD事件而经历电阻的非易失性变化，使得电阻器在ESD事件消散之后保持电阻的变化。 结果，通过在半导体制造过程中的一个或多个步骤之后监视ESD敏感电阻器的电阻，可以检测到ESD事件的发生，并且在一些情况下，ESD事件的幅度。