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    FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE
    61.
    发明申请
    FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE 有权
    半导体非易失性存储器件的制造方法和结构

    公开(公告)号：US20100135080A1

    公开(公告)日：2010-06-03

    申请号：US12648796

    申请日：2009-12-29

    Applicant: Digh HISAMOTO ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    Inventor： Digh HISAMOTO ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    IPC: G11C16/04 ,  H01L29/792

    CPC classification number: H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

    Abstract: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

    Abstract translation: 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

    Integrated semiconductor nonvolatile storage device
    62.
    发明授权
    Integrated semiconductor nonvolatile storage device 有权
    集成半导体非易失性存储装置

    公开(公告)号：US07723779B2

    公开(公告)日：2010-05-25

    申请号：US11437610

    申请日：2006-05-22

    Applicant: Digh Hisamoto ,  Shin'ichiro Kimura ,  Daiske Okada ,  Kan Yasui

    Inventor： Digh Hisamoto ,  Shin'ichiro Kimura ,  Daiske Okada ,  Kan Yasui

    IPC: H01L21/336

    CPC classification number: H01L27/115 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/792

    Abstract: An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times.In the case of conventional nonvolatile semiconductor storage devices having a split-gate structure, there is a tradeoff between the read current and the maximum allowable number of reprogramming operations. To overcome this problem, an integrated semiconductor nonvolatile storage device of the present invention is configured such that memory cells having different memory gate lengths are integrated on the same chip. This allows the device to be read at high speed and reprogrammed an increased number of times.

    Abstract translation: 本发明的目的是提供一种能够高速读取并重新编程次数增加的集成半导体非易失性存储装置。 在具有分割栅结构的常规非易失性半导体存储器件的情况下，读取电流和最大可允许重编程操作次数之间存在权衡。 为了克服这个问题，本发明的集成半导体非易失性存储装置被配置为使得具有不同存储器栅极长度的存储单元集成在同一芯片上。 这允许以高速读取设备并重新编程增加的次数。

    DIFFERENTIAL HEAD HAVING A BALANCED OUTPUT AND METHOD OF MANUFACTURING THEREOF
    63.
    发明申请
    DIFFERENTIAL HEAD HAVING A BALANCED OUTPUT AND METHOD OF MANUFACTURING THEREOF 有权
    具有平衡输出的差分头及其制造方法

    公开(公告)号：US20100118448A1

    公开(公告)日：2010-05-13

    申请号：US12615221

    申请日：2009-11-09

    Applicant: Kan Yasui ,  Masato Shiimoto ,  Takeshi Nakagawa ,  Hiroyuki Katada ,  Nobuo Yoshida ,  Hiroyuki Hoshiya

    Inventor： Kan Yasui ,  Masato Shiimoto ,  Takeshi Nakagawa ,  Hiroyuki Katada ,  Nobuo Yoshida ,  Hiroyuki Hoshiya

    IPC: G11B5/127

    CPC classification number: G11B5/3163 ,  G11B5/398

    Abstract: In one embodiment, a differential-type magnetic read head includes a differential-type magneto-resistive-effect film formed on a substrate, and a pair of electrodes for applying current in a direction perpendicular to a film plane of the film. The film includes a first and second stacked film, each having a pinned layer, an intermediate layer, and a free layer, with the second stacked film being formed on the first stacked film. A side face in a track width direction of the film is shaped to have an inflection point at an intermediate position in a thickness direction of the film, and the side face is shaped to be approximately vertical to the substrate in an upward direction of the substrate from the inflection point. Also, the side face is shaped to be gradually increased in track width as approaching the substrate in a downward direction of the substrate from the inflection point.

    Abstract translation: 在一个实施例中，差分型磁读头包括形成在基板上的差分型磁阻效应膜和用于在垂直于膜的膜平面的方向上施加电流的一对电极。 膜包括第一和第二堆叠膜，每个具有钉扎层，中间层和自由层，第二堆叠膜形成在第一堆叠膜上。 膜的轨道宽度方向的侧面成形为在膜的厚度方向上的中间位置具有拐点，并且侧面成形为在基板的上方大致垂直于基板 从拐点。 此外，侧面被成形为在从拐点向基板向下方向接近基板的轨迹宽度上逐渐增加。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    67.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号：US20080265286A1

    公开(公告)日：2008-10-30

    申请号：US12109340

    申请日：2008-04-24

    Applicant: Tetsuya ISHIMARU ,  Yasuhiro Shimamoto ,  Toshiyuki Mine ,  Yasunobu Aoki ,  Koichi Toba ,  Kan Yasui

    Inventor： Tetsuya ISHIMARU ,  Yasuhiro Shimamoto ,  Toshiyuki Mine ,  Yasunobu Aoki ,  Koichi Toba ,  Kan Yasui

    IPC: H01L29/76

    CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/66833

    Abstract: A memory cell includes an ONO film composed of a stacked film of a silicon nitride film SIN which is a charge trapping portion and oxide films BOTOX and TOPOX positioned under and over the silicon nitride film, a memory gate electrode MG over the ONO film, a source region MS, and a drain region MD, and program or erase is performed by hot carrier injection in the memory cell. In the memory cell, a total concentration of N—H bonds and Si—H bonds contained in the silicon nitride film SIN is made to be 5×1020 cm−3 or less.

    Abstract translation: 存储单元包括由作为电荷捕获部分的氮化硅膜SIN和位于氮化硅膜下面的氧化物膜BOTOX和TOPOX的叠层膜，ONO膜上的存储栅电极MG， 源区MS和漏区MD，并且通过在存储单元中的热载流子注入来执行编程或擦除。 在存储单元中，氮化硅膜Sin中包含的N-H键和Si-H键的总浓度为5×10 20 -3 -3以下。

    Fabrication method and structure of semiconductor non-volatile memory device
    69.
    发明申请
    Fabrication method and structure of semiconductor non-volatile memory device 有权
    半导体非易失性存储器件的制造方法和结构

    公开(公告)号：US20070040208A1

    公开(公告)日：2007-02-22

    申请号：US11589095

    申请日：2006-10-30

    Applicant: Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    Inventor： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    IPC: H01L29/76

    CPC classification number: H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

    Abstract: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

    Abstract translation: 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

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