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    Magnetic memory adopting synthetic antiferromagnet as free magnetic layer
    61.
    发明授权
    Magnetic memory adopting synthetic antiferromagnet as free magnetic layer 有权
    磁记忆采用合成反铁磁体作为自由磁性层

    公开(公告)号：US07242047B2

    公开(公告)日：2007-07-10

    申请号：US11208370

    申请日：2005-08-19

    申请人： Kaoru Mori ,  Tetsuhiro Suzuki ,  Yoshiyuki Fukumoto ,  Sadahiko Miura

    发明人： Kaoru Mori ,  Tetsuhiro Suzuki ,  Yoshiyuki Fukumoto ,  Sadahiko Miura

    IPC分类号： H01L29/76

    CPC分类号： G11C11/16 ,  B82Y25/00 ,  H01F10/3254 ,  H01F10/3272 ,  H01L43/08

    摘要： A magnetic memory is composed of: a magnetoresistance element including a free magnetic layer; a first interconnection extending in a first direction obliquely to an easy axis of the free magnetic layer; a second interconnection extending in a second direction substantially orthogonal to the first direction; and a write circuit writing data into the free magnetic layer through developing a first write current on the first interconnection, and then developing a second write current on the second interconnection with the first write current turned on. The free magnetic layer includes: first to N-th ferromagnetic layers and first to (N−1)-th non-magnetic layers with N being equal to or more than 4, the i-th non-magnetic layer being disposed between the i-th and (i+1)-th ferromagnetic layers with i being any of natural numbers equal to or less than N−1. The free magnetic layer is designed so that antiferromagnetic coupling(s) between the j-th and (j+1)-th ferromagnetic layers is stronger than that between the first and second ferromagnetic layers, j being any of integers ranging from 2 to N−2.

    摘要翻译： 磁存储器包括：包括自由磁性层的磁阻元件; 第一互连件，其在第一方向上倾斜于所述自由磁性层的容易轴线延伸; 沿与第一方向大致正交的第二方向延伸的第二互连; 以及写入电路，通过在所述第一互连上形成第一写入电流将数据写入所述自由磁性层，然后在所述第二互连上开启第二写入电流，所述第一写入电流导通。 自由磁性层包括：第一至第N铁磁层和N等于或大于4的第一至第（N-1）个非磁性层，第i个非磁性层设置在i 和第（i + 1）个铁磁层，其中i为等于或小于N-1的任意自然数。 自由磁性层被设计成使得第j和第（j + 1）个铁磁层之间的反铁磁耦合比第一和第二铁磁层之间的反铁磁耦合更强，j是从2到N的整数中的任何一个 -2。

    Semiconductor memory device with shift register-based refresh address generation circuit
    62.
    发明授权
    Semiconductor memory device with shift register-based refresh address generation circuit 有权
    具有基于移位寄存器的刷新地址产生电路的半导体存储器件

    公开(公告)号：US07145825B2

    公开(公告)日：2006-12-05

    申请号：US10800831

    申请日：2004-03-16

    申请人： Kaoru Mori ,  Katuhiro Mori ,  Shinichi Yamada ,  Kuninori Kawabata ,  Shigemasa Ito

    发明人： Kaoru Mori ,  Katuhiro Mori ,  Shinichi Yamada ,  Kuninori Kawabata ,  Shigemasa Ito

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406

    摘要： A semiconductor memory device with low power consumption in driving control signals of shift registers. The device contains a plurality of memory cell arrays each composed of a predetermined number of rows of memory cells. One set of shift registers are coupled to each cell array, and the nth set of shift registers successively activate word line selection signals according to a given control signal, so that the corresponding word lines of the nth cell array will be refreshed. Also coupled to each cell array is a shift register controller. The nth shift register controller provides a control signal to the nth set of shift registers when the nth cell array is being refreshed. When the refresh of that cell array is finished, the nth shift register controller forwards the control signal to the (n+1)th set of shift registers, thus initiating refresh operation for the (n+1)th cell array.

    摘要翻译： 一种在移位寄存器的驱动控制信号中具有低功耗的半导体存储器件。 该装置包含多个存储单元阵列，每个存储单元阵列由预定数量的存储单元行组成。 一组移位寄存器耦合到每个单元阵列，并且第n组移位寄存器根据给定的控制信号依次激活字线选择信号，使得第n个单元阵列的相应字线将被刷新。 还耦合到每个单元阵列是移位寄存器控制器。 当第n个单元阵列被刷新时，第n个移位寄存器控制器向第n组移位寄存器提供控制信号。 当完成该单元阵列的刷新时，第n移位寄存器控制器将控制信号转发到第（n + 1）个移位寄存器组，从而启动第（n + 1）个单元阵列的刷新操作。

    Semiconductor memory device capable of driving non-selected word lines to first and second potentials
    63.
    发明申请
    Semiconductor memory device capable of driving non-selected word lines to first and second potentials 失效
    能够将未选择的字线驱动到第一和第二电位的半导体存储器件

    公开(公告)号：US20060098523A1

    公开(公告)日：2006-05-11

    申请号：US11313963

    申请日：2005-12-22

    申请人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

    发明人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

    IPC分类号： G11C8/00

    CPC分类号： G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

    摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

    摘要翻译： 半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平 在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。 此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量 当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量 存储单元阵列。 此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡 电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

    Semiconductor memory having memory cells requiring refresh operation
    64.
    发明授权
    Semiconductor memory having memory cells requiring refresh operation 失效
    具有需要刷新操作的存储单元的半导体存储

    公开(公告)号：US06834021B2

    公开(公告)日：2004-12-21

    申请号：US10350191

    申请日：2003-01-24

    申请人： Kaoru Mori ,  Shinichi Yamada

    发明人： Kaoru Mori ,  Shinichi Yamada

    IPC分类号： G11C700

    CPC分类号： G11C11/406

    摘要： An operation control circuit sets an inactivating timing of sense amplifiers activated in response to a read request, a write request, or a refresh request, to the timing a maximum possible quantity of signals which can be output from the sense amplifiers operating in response to the refresh request is transmitted to memory cells. Tailoring the activating period of the sense amplifiers to a refresh operation can reduce access time. A refresh control circuit generates a predetermined number of refresh requests consecutively to refresh all of the memory cells before extending the cycle of generating refresh requests. When refresh requests occur consecutively, the refresh frequency can be lowered to reduce power consumption. As a result, access time can be reduced without increasing power consumption during the standby mode.

    摘要翻译： 操作控制电路将响应于读取请求，写入请求或刷新请求而被激活的读出放大器的失活定时设置为能够响应于所述读取放大器操作的读出放大器输出的最大可能量的信号的定时 刷新请求被传送到存储单元。 将感测放大器的激活周期调整到刷新操作可以减少访问时间。 刷新控制电路在扩展生成刷新请求的周期之前，连续生成预定数量的刷新请求以刷新所有存储单元。 当刷新请求连续发生时，可以降低刷新频率以降低功耗。 结果，可以在待机模式期间不增加功耗来降低访问时间。

    N-aryloxyacyl-n-phenyltetrahydrophthalamic acid derivatives, methods of producing same, and herbicides containing same as effective components
    66.
    发明授权
    N-aryloxyacyl-n-phenyltetrahydrophthalamic acid derivatives, methods of producing same, and herbicides containing same as effective components 失效
    N-芳氧基酰基 - 正苯基四氢酞酸衍生物，其制备方法和含有与有效成分相同的除草剂

    公开(公告)号：US5481022A

    公开(公告)日：1996-01-02

    申请号：US256646

    申请日：1994-07-19

    申请人： Tetsuo Takematsu ,  Takashi Kume ,  Shoji Yamaoka ,  Takeo Komata ,  Kiyoshi Suzuki ,  Yukio Ikeda ,  Matsue Kawamura ,  Yumiko Koda ,  Kaoru Mori

    发明人： Tetsuo Takematsu ,  Takashi Kume ,  Shoji Yamaoka ,  Takeo Komata ,  Kiyoshi Suzuki ,  Yukio Ikeda ,  Matsue Kawamura ,  Yumiko Koda ,  Kaoru Mori

    IPC分类号： A01N37/30 ,  A01N37/36 ,  A01N37/38 ,  C07C231/08 ,  C07C233/92 ,  C07C235/68 ,  C07C235/88 ,  C07C257/02 ,  C07C229/38 ,  A01N37/10

    CPC分类号： C07C235/88 ,  A01N37/36 ,  A01N37/38 ,  C07C235/68 ,  C07C257/02 ,  C07C2101/16

    摘要： The invention provides N-aryloxyacyl-N-phenyltetrahydrophthalamic acid derivatives represented by the general formula [I], a method of producing the same, and a herbicide containing the same as the effective components, ##STR1## wherein X and Y each individually represent hydrogen atoms or halogen atoms, Ar represents a substituted or unsubstituted phenyl group or naphthyl group, R.sup.1 represents a hydrogen atom, a halogen atom, a lower alkyl group, a lower alkoxy group, a lower alkenyloxy group, a lower alkynyloxy group, a lower alkoxyalkoxy group or a lower alkoxycarbonylalkoxy group, R.sup.2 represents a hydrogen atom or a lower alkyl group, R.sup.3 represents a hydroxyl, a lower alkoxy group, a lower alkenyloxy group, a lower alkynyloxy group, a lower alkoxyalkoxy group, a benzyloxy group or a lower alkoxycarbonylalkoxy group, and m is an integer ranging from 0 to 5. This herbicide which is very useful can be widely applied to upland, paddy field, orchard, turf, forest, non-crop land, etc., and is not harmful to crops.

    摘要翻译： PCT No.PCT / JP93 / 01756 Sec。 371日期：1994年7月19日 102（e）日期1994年7月19日PCT 1993年12月2日PCT公布。 公开号WO94 / 12469 日期：1994年6月9日本发明提供由通式[I]表示的N-芳氧基酰基-N-苯基四氢酞酸衍生物，其制备方法和含有与有效成分相同的除草剂， I]其中X和Y各自独立地表示氢原子或卤原子，Ar表示取代或未取代的苯基或萘基，R1表示氢原子，卤素原子，低级烷基，低级烷氧基，低级烯氧基 低级烷氧基，低级烷氧基烷氧基或低级烷氧羰基烷氧基，R2表示氢原子或低级烷基，R3表示羟基，低级烷氧基，低级链烯氧基，低级炔氧基，低级烷氧基 烷氧基烷氧基，苄氧基或低级烷氧基羰基烷氧基，m为0〜5的整数。该除草剂非常有用，可广泛应用于高地，水田，果园，草坪，森林， - 耕地等，对作物无害。

    Semiconductor memory
    68.
    发明授权
    Semiconductor memory 有权
    半导体存储器

    公开(公告)号：US08385128B2

    公开(公告)日：2013-02-26

    申请号：US13020636

    申请日：2011-02-03

    申请人： Kaoru Mori ,  Toshiya Uchida

    发明人： Kaoru Mori ,  Toshiya Uchida

    IPC分类号： G11C16/06

    CPC分类号： G11C16/26 ,  G11C7/18 ,  G11C7/227 ,  G11C16/24 ,  G11C16/32

    摘要： A semiconductor memory includes a sense amplifier which operates in response to activation of a sense amplifier enable signal and determines logic held in a nonvolatile memory cell according to a voltage of a bit line, the voltage varying with a cell current flowing through a real cell transistor, a replica cell transistor coupled in series between a first node and a ground line, and a timing generation unit. The timing generation unit activates the sense amplifier enable signal when the first node coupled to the ground line via the replica cell transistor changes from a high level to a low level. The replica cell transistor includes a control gate receiving a constant voltage and a floating gate coupled to the control gate. Thus, the activation timing of the sense amplifier can be optimally set in accordance with the electric characteristic of the memory cell.

    摘要翻译： 半导体存储器包括读出放大器，其响应于读出放大器使能信号的激活而操作，并且根据位线的电压确定保持在非易失性存储器单元中的逻辑，该电压随着流过真实单元晶体管的单元电流而变化 耦合在第一节点和地线之间的复制单元晶体管，以及定时产生单元。 当通过复制单元晶体管耦合到接地线的第一节点从高电平变为低电平时，定时生成单元激活读出放大器使能信号。 复制单元晶体管包括接收恒定电压的控制栅极和耦合到控制栅极的浮置栅极。 因此，可以根据存储单元的电特性来最佳地设置读出放大器的激活定时。

    Semiconductor memory and method for testing the same
    69.
    发明授权
    Semiconductor memory and method for testing the same 有权
    半导体存储器及其测试方法

    公开(公告)号：US08276027B2

    公开(公告)日：2012-09-25

    申请号：US13050633

    申请日：2011-03-17

    申请人： Kaoru Mori

    发明人： Kaoru Mori

    IPC分类号： G11C29/00

    CPC分类号： G11C29/16 ,  G11C2029/1804

    摘要： A semiconductor memory in which arbitrary operation mode information is set in a plurality of CRs at test time and by which a test cost is reduced and a method for testing such a semiconductor memory. The plurality of CRs hold operation mode information. When a CR control circuit detects write commands to write to an address for register access or read commands to read from the address for register access in a predetermined order, the CR control circuit updates the operation mode information for each of the plurality of CRs on a time division basis. A command generation section generates the write commands, the read commands, or a test start command by which write operation or read operation does not occur, in response to a control signal from the outside. In addition, the command generation section regenerates the test start command each time the plurality of CRs are updated. A data pad compression circuit changes the operation mode information to be written to the plurality of CRs by using test data inputted to part of data pads, after inverting the test data or in its original condition according to a code, as data for a rest of the data pads, the code represented by part of an address inputted at the time of the test start command being sent.

    摘要翻译： 一种半导体存储器，其中在测试时间内在多个CR中设置任意操作模式信息，并且测试成本降低，并且测试这种半导体存储器的方法。 多个CR保持操作模式信息。 当CR控制电路检测写入命令以写入寄存器访问的地址或读取命令以按预定顺序从地址读取寄存器访问时，CR控制电路更新在多个CR中的每一个的操作模式信息 时分基础。 响应于来自外部的控制信号，命令生成部分生成写入命令，读取命令或者不发生写入操作或读取操作的测试开始命令。 另外，每当更新多个CR时，命令生成部重新生成测试开始命令。 数据块压缩电路通过使用输入到数据块的一部分的测试数据，在将测试数据或其原始状态根据代码反转之后，将待写入的操作模式信息改变为用于其余部分的数据 数据焊盘，由发送测试开始命令时输入的地址的一部分表示的代码。