公开(公告)号：US6097660A

公开(公告)日：2000-08-01

申请号：US53511

申请日：1998-04-02

申请人： Kenji Tsuchida ,  Shinichiro Shiratake ,  Tsuneo Inaba

发明人： Kenji Tsuchida ,  Shinichiro Shiratake ,  Tsuneo Inaba

IPC分类号： G11C11/401 ,  G11C5/02 ,  G11C8/12 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C5/025 ,  G11C11/4097 ,  G11C8/12

摘要： A semiconductor memory device comprises a plurality of memory banks each having a plurality of memory cell arrays and a plurality of sense amplifiers such that the memory cell arrays and the sense amplifiers are alternately disposed in a first direction, the memory banks being disposed in a second direction perpendicular to the first direction, a plurality of row decoders respectively provided in the first direction for the plurality of memory banks, a column decoder provided in the second direction with respect to the plurality of memory banks, a plurality of first data lines respectively provided in the second direction for the plurality of memory banks, and connected with the plurality of sense amplifiers in accordance with a signal outputted from the column decoder, a plurality of second data lines provided in the second direction, penetrating through the plurality of memory banks, and shared by the plurality of first data lines disposed for the plurality of memory banks, and a plurality of switching elements each having a first end connected to one of the plurality of first data lines and a second end connected to one of the plurality of second data lines, and controlled by a bank activation signal of a memory bank corresponding to the first data line connected to the first ends.

摘要翻译： 半导体存储器件包括多个存储器组，每个存储器组具有多个存储单元阵列和多个读出放大器，使得存储单元阵列和读出放大器交替地沿第一方向设置，存储体设置在第二 分别设置在多个存储体的第一方向的多个行解码器，相对于多个存储体设置在第二方向上的列解码器，分别设置有多个第一数据线 在所述多个存储体的第二方向上，并且根据从所述列解码器输出的信号与所述多个读出放大器连接;沿着所述第二方向设置的穿过所述多个存储体的多个第二数据线， 并且由为多个存储体设置的多个第一数据线和plu共享 开关元件的强度各自具有连接到多个第一数据线之一的第一端和连接到所述多条第二数据线之一的第二端，并且由对应于第一数据的存储体的存储体激活信号控制 线连接到第一端。

公开(公告)号：US6094390A

公开(公告)日：2000-07-25

申请号：US72724

申请日：1998-05-06

申请人： Tsuneo Inaba ,  Shinichiro Shiratake ,  Kenji Tsuchida

发明人： Tsuneo Inaba ,  Shinichiro Shiratake ,  Kenji Tsuchida

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： H01L27/10897 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/18

摘要： A semiconductor memory device with a semiconductor substrate and a plurality of element regions formed in the semiconductor is shown. The semiconductor memory device further includes at least one column gate and at least one equalizer in which they are formed as a set in at least one of the element regions.

摘要翻译： 示出了半导体衬底和半导体中形成的多个元件区的半导体存储器件。 半导体存储器件还包括至少一个列栅极和至少一个均衡器，其中它们在至少一个元件区域中形成为一组。

公开(公告)号：US5933051A

公开(公告)日：1999-08-03

申请号：US714291

申请日：1996-09-18

申请人： Kenji Tsuchida ,  Yoshio Okada

发明人： Kenji Tsuchida ,  Yoshio Okada

IPC分类号： H03F3/343 ,  G05F3/24 ,  G11C5/14 ,  G11C11/407 ,  G05F3/02

CPC分类号： G05F3/242 ,  G05F3/24 ,  G11C5/147

摘要： A constant voltage generating device comprises a reference voltage generating circuit, a constant-current circuit unit and a current-to-voltage converting circuit unit. The reference voltage generating circuit generates a desired reference voltage. The constant-current circuit unit comprises a differential error amplifier to which the reference voltage generated by the reference voltage generating circuit is input as a reference potential, a first current controlling MOS transistor having a gate electrode to which an output of the differential amplifier is input, and a standard resistor serially connected to the first current controlling MOS transistor. The constant-current circuit unit generates a reference current to control a differential amplifier so that a constant current can be caused to flow therethrough. The current-to-voltage converting unit comprises a second current controlling MOS transistor constituting a current mirror together with the first current controlling MOS transistor of the constant-current circuit unit, and a current-to-voltage converting MOS transistor serially connected to the second current controlling MOS transistor and constituting a current mirror together with an active element unit current controlling MOS transistor of the differential amplifier.

摘要翻译： 恒压发生装置包括参考电压产生电路，恒流电路单元和电流 - 电压转换电路单元。 参考电压产生电路产生期望的参考电压。 恒流电路单元包括差分误差放大器，由基准电压产生电路产生的参考电压输入到该参考电压作为参考电位;第一电流控制MOS晶体管，具有输入差分放大器的输入端的栅电极 以及串联连接到第一电流控制MOS晶体管的标准电阻器。 恒流电路单元产生参考电流以控制差分放大器，使得可以使恒定电流流过。 电流 - 电压转换单元包括与恒流电路单元的第一电流控制MOS晶体管一起构成电流镜的第二电流控制MOS晶体管和串联连接到第二电流控制MOS晶体管的电流 - 电压转换MOS晶体管 电流控制MOS晶体管，并与差分放大器的有源元件单元电流控制MOS晶体管一起构成电流镜。

公开(公告)号：US5859805A

公开(公告)日：1999-01-12

申请号：US832818

申请日：1997-04-04

申请人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

发明人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

IPC分类号： G11C7/06 ,  G11C11/4091 ,  H01L27/108 ,  G11C5/02

CPC分类号： G11C7/065 ,  G11C11/4091 ,  H01L27/108

摘要： A dynamic semiconductor memory device is made up of a plurality of dynamic memory cells arrayed along a plurality of bit line pairs, and a plurality of dynamic sense amplifiers associated with the plurality of bit line pairs, each sense amplifier having a pair of MOS transistors connected to a corresponding pair of bit lines. In one embodiment, the first and second transistors of one of the sense amplifiers and the first and second transistors of another sense amplifier adjacent thereto are positioned within a region defined by two adjacent pairs of bit lines. Each of the bit line pairs has first and second bit lines extending in a first direction perpendicular to a second direction in which the source and drain regions are formed in the semiconductor substrate so that the transistors of the sense amplifiers are arranged one for every four bit lines in the second direction.

公开(公告)号：US5644525A

公开(公告)日：1997-07-01

申请号：US272284

申请日：1994-07-08

申请人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

发明人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

IPC分类号： G11C7/06 ,  G11C11/4091 ,  H01L27/108 ,  G11C5/02 ,  G11C11/407 ,  G11C11/413

CPC分类号： G11C7/065 ,  G11C11/4091 ,  H01L27/108

摘要： A dynamic semiconductor memory device is made up of a plurality of dynamic memory cells arrayed along a plurality of bit line pairs, and a plurality of dynamic sense amplifiers associated with the plurality of bit line pairs, each sense amplifier having a pair of MOS transistors connected to a corresponding pair of bit lines. In one embodiment, the first and second transistors of one of the sense amplifiers and the first and second transistors of another sense amplifier adjacent thereto are positioned within a region defined by two adjacent pairs of bit lines. Each of the bit line pairs has first and second bit lines extending in a first direction perpendicular to a second direction in which the source and drain regions are formed in the semiconductor substrate so that the transistors of the sense amplifiers are arranged one for every four bit lines in the second direction.

摘要翻译： 动态半导体存储器件由沿着多个位线对排列的多个动态存储器单元和与多个位线对相关联的多个动态读出放大器组成，每个读出放大器具有连接的一对MOS晶体管 到相应的一对位线。 在一个实施例中，读出放大器之一的第一和第二晶体管和与其相邻的另一个读出放大器的第一和第二晶体管位于由两个相邻的位线对限定的区域内。 每个位线对具有在与第二方向垂直的第一方向上延伸的第一和第二位线，其中源极和漏极区域形成在半导体衬底中，使得读出放大器的晶体管每四位排列一个 线在第二个方向。

公开(公告)号：US5289413A

公开(公告)日：1994-02-22

申请号：US712106

申请日：1991-06-07

申请人： Kenji Tsuchida ,  Yohji Watanabe

发明人： Kenji Tsuchida ,  Yohji Watanabe

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1033 ,  G11C7/1006

摘要： A MOS memory device includes an array of rows and columns of memory cells, word lines connected to the rows of memory cells, and a plurality of pairs of bits lines connected to the columns. Sense amplifiers and transfer gates are provided for every bit line pair. A column decoder has outputs connected via column-select lines to transfer gates such that each output is connected to two adjacent gates. When activating a certain column, the column decoder potentially activates another column adjacent to the certain column before actually receiving the corresponding column address. This permits information bits stored in four memory cells to be transferred simultaneously to the registers and latched therein. A multiplexer serially reads out the latched information bits. The column preactivation improves the serial accessing speed of the memory device.

摘要翻译： MOS存储器件包括存储器单元的行和列的阵列，连接到存储器单元的行的字线以及连接到列的多对位线。 为每个位线对提供感测放大器和传输门。 列解码器具有通过列选择线连接的输出以传送门，使得每个输出连接到两个相邻的门。 当激活某个列时，列解码器在实际接收相应的列地址之前潜在地激活与特定列相邻的另一列。 这允许存储在四个存储单元中的信息位同时传送到寄存器并锁存在其中。 多路复用器串行读出锁存的信息位。 列预激活提高了存储设备的串行访问速度。

公开(公告)号：US5144583A

公开(公告)日：1992-09-01

申请号：US461121

申请日：1990-01-04

申请人： Yukihito Oowaki ,  Kenji Tsuchida ,  Daisaburo Takashima

发明人： Yukihito Oowaki ,  Kenji Tsuchida ,  Daisaburo Takashima

IPC分类号： G11C11/4097 ,  H01L23/528 ,  H01L27/108

CPC分类号： H01L27/10805 ,  G11C11/4097 ,  H01L23/528 ,  H01L2924/0002

摘要： A dynamic random-access memory has bit-line pairs, word lines intersecting with the bit-line pairs, and memory cells arranged at the intersections of the bit-line pairs and the word lines, and sense amplifiers provided for the bit-line pairs, respectively. One of every two neighboring bit-line pairs is twisted at one portion, thus forming a twisted crossing section. The twisted crossing section is made of the parts of the gate electrodes of the transistors incorporated in the sense amplifier connected to the twisted bit-line pair. The bit-line pairs is twisted at a portion substantially middle with respect to the direction in which it extends, and the sensr amplifier associated with this bit-line pair is located at the twisted portion thereof.

摘要翻译： 动态随机存取存储器具有位线对，与位线对相交的字线和布置在位线对和字线的交点处的存储单元，以及为位线对提供的读出放大器 ， 分别。 每两个相邻位线对中的一个在一部分被扭曲，从而形成扭曲的交叉部分。 扭转交叉部分由连接到扭绞位线对的读出放大器中的晶体管的栅电极的部分构成。 位线对在相对于其延伸的方向大致中间的部分处扭曲，并且与该位线对相关联的感应放大器位于其扭曲部分处。

公开(公告)号：US5062079A

公开(公告)日：1991-10-29

申请号：US412930

申请日：1989-09-26

申请人： Kenji Tsuchida ,  Yukihito Oowaki

发明人： Kenji Tsuchida ,  Yukihito Oowaki

IPC分类号： G11C11/4091 ,  G11C11/4097

CPC分类号： G11C11/4097 ,  G11C11/4091

摘要： A MOS type random access memory disclosed has a plurality of pairs of sequentially aligned folded type bit lines each of which has a first bit line and a second bit line. Memory cells are arranged at points of intersection between a memory cell word line and the first bit lines. Dummy cells are arranged at points of intersection of a dummy cell word line and the second bit lines. Sense amplifier circuits are connected to the bit line pairs, respectively. In a data read mode of the memory, when a bit data is read from a certain memory cell which is connected to a first word line selected and a first bit line of a selected bit line pair, a second bit line onto which a data voltage is read from a dummy cell of the selected bit line pair is forcedly fixed to a precharge voltage produced by a precharge voltage generator in a presented time interval after the first word line is selected and before a certain sense amplifier circuit connected to the selected bit line pair gets activated, whereby interference noise may be eliminated which is introduced onto the selected bit line pair from a bit line pair adjacent to the selected bit line pair.

摘要翻译： 所公开的MOS型随机存取存储器具有多对顺序排列的折叠型位线，每个位线具有第一位线和第二位线。 存储单元布置在存储单元字线和第一位线之间的交点处。 虚拟单元被布置在虚拟单元字线和第二位线的交点处。 感测放大器电路分别连接到位线对。 在存储器的数据读取模式中，当从连接到所选位置的第一字线和选定位线对的第一位线的特定存储器单元读取位数据时，将数据电压 从所选择的位线对的虚拟单元中读取的数据被强制地固定在由预充电电压发生器产生的预充电电压之后，在选择第一字线之后的所呈现的时间间隔内，并且在连接到所选择的位线之前的某个读出放大器电路 对可以被激活，由此可以消除干扰噪声，其从与所选位线对相邻的位线对引入到所选位线对上。

公开(公告)号：US09613671B2

公开(公告)日：2017-04-04

申请号：US14692239

申请日：2015-04-21

申请人： Yutaka Shirai ,  Naoki Shimizu ,  Kenji Tsuchida ,  Yoji Watanabe ,  Ji Hyae Bae ,  Yong Ho Kim

发明人： Yutaka Shirai ,  Naoki Shimizu ,  Kenji Tsuchida ,  Yoji Watanabe ,  Ji Hyae Bae ,  Yong Ho Kim

IPC分类号： G11C8/00 ,  G11C8/18 ,  G11C7/12 ,  G11C8/10 ,  G11C8/12 ,  G11C11/16 ,  G11C7/10

CPC分类号： G11C7/12 ,  G11C7/1039 ,  G11C7/222 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

摘要： According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.

公开(公告)号：US08482969B2

公开(公告)日：2013-07-09

申请号：US13228255

申请日：2011-09-08

申请人： Katsuhiko Hoya ,  Kenji Tsuchida

发明人： Katsuhiko Hoya ,  Kenji Tsuchida

IPC分类号： G11C11/00

CPC分类号： G11C11/1693 ,  G11C11/1675

摘要： A memory according to an embodiment includes bit lines, word lines, source lines, magnetic tunnel junction elements and transistors that are serially connected between the bit lines and the source lines, respectively, and a sense amplifier that detects data stored in the magnetic tunnel junction elements. The semiconductor storage device includes multiplexers between the bit lines and the sense amplifier in order to select one of the bit lines to be connected to the sense amplifier, and write amplifiers that are located corresponding to memory cell blocks each of which includes memory cells each including the magnetic tunnel junction element and the transistor and are connected to the bit lines or connected via the multiplexers to the bit lines. To write data, the sense amplifier applies a write voltage to the bit lines and then the write amplifiers hold the write voltage.

摘要翻译： 根据实施例的存储器分别包括位线和源极线之间串联连接的位线，字线，源极线，磁性隧道结元件和晶体管，以及检测放大器，其检测存储在磁性隧道结中的数据 元素。 半导体存储装置包括位线和读出放大器之间的多路复用器，以便选择要连接到读出放大器的位线之一，以及对应于存储单元块的写入放大器，每个存储单元块包括各自包括 磁性隧道结元件和晶体管，并且连接到位线或经由多路复用器连接到位线。 为了写入数据，读出放大器向位线施加写入电压，然后写入放大器保持写入电压。