Nonvolatile memory device and methods of operating and fabricating the same
    64.
    发明授权
    Nonvolatile memory device and methods of operating and fabricating the same 有权
    非易失存储器件及其操作和制造方法

    公开(公告)号:US07872249B2

    公开(公告)日:2011-01-18

    申请号:US11723018

    申请日:2007-03-15

    IPC分类号: H01L47/00

    摘要: Provided is a nonvolatile memory device and method of operating and fabricating the same for higher integration and higher speed, while allowing for a lower operating current. The nonvolatile memory device may include a semiconductor substrate. Resistive layers each storing a variable resistive state may be formed on the surface of the semiconductor substrate. Buried electrodes may be formed on the semiconductor substrate under the resistive layers and may connect to the resistive layers. Channel regions may be formed on the surface of the semiconductor substrate and connect adjacent resistive layers to each other, but not to the buried electrodes. Gate insulating layers may be formed on the channel regions of the semiconductor substrate. Gate electrodes may be formed on the gate insulating layers and extend over the resistive layers.

    摘要翻译: 提供了一种非易失性存储器件及其操作和制造方法,用于更高的集成度和更高的速度,同时允许较低的工作电流。 非易失性存储器件可以包括半导体衬底。 各自存储可变电阻状态的电阻层可以形成在半导体衬底的表面上。 掩埋电极可以形成在半导体衬底下的电阻层下,并且可以连接到电阻层。 通道区域可以形成在半导体衬底的表面上,并且将相邻的电阻层彼此连接,而不是埋入电极。 栅极绝缘层可以形成在半导体衬底的沟道区上。 栅电极可以形成在栅极绝缘层上并在电阻层上延伸。

    Transistor and method of operating transistor
    67.
    发明授权
    Transistor and method of operating transistor 失效
    晶体管及晶体管工作方式

    公开(公告)号:US07414295B2

    公开(公告)日:2008-08-19

    申请号:US11274475

    申请日:2005-11-16

    IPC分类号: H01L29/8605 G11C11/00

    CPC分类号: H01L29/685

    摘要: A transistor in which a physical property of its channel is changed according to an applied voltage, and methods of manufacturing and operating the same are provided. The transistor may include a first conductive layer on a substrate, a phase change layer and a second conductive layer which are sequentially stacked on the first conductive layer, a first current direction limiting unit and a second current direction limiting unit formed on the second conductive layer by being separated within a space, a third conductive layer and a fourth conductive layer formed on the first current direction limiting unit and the second current direction limiting unit, respectively, a word line connected to the third conductive layer, a bit line connected to the fourth conductive layer, and a voltage lowering unit connected to the word line.

    摘要翻译: 提供其通道的物理特性根据施加的电压而改变的晶体管,并且提供其制造和操作方法。 晶体管可以包括基板上的第一导电层,相继层叠在第一导电层上的相变层和第二导电层,形成在第二导电层上的第一电流方向限制单元和第二电流方向限制单元 通过在空间内分离,分别形成在第一电流方向限制单元和第二电流方向限制单元上的第三导电层和第四导电层,连接到第三导电层的字线,连接到第三导电层的位线 第四导电层和连接到字线的降压单元。

    Nonvolatile memory device and methods of operating and fabricating the same
    69.
    发明申请
    Nonvolatile memory device and methods of operating and fabricating the same 有权
    非易失存储器件及其操作和制造方法

    公开(公告)号:US20080012064A1

    公开(公告)日:2008-01-17

    申请号:US11723018

    申请日:2007-03-15

    IPC分类号: H01L29/76

    摘要: Provided is a nonvolatile memory device and method of operating and fabricating the same for higher integration and higher speed, while allowing for a lower operating current. The nonvolatile memory device may include a semiconductor substrate. Resistive layers each storing a variable resistive state may be formed on the surface of the semiconductor substrate. Buried electrodes may be formed on the semiconductor substrate under the resistive layers and may connect to the resistive layers. Channel regions may be formed on the surface of the semiconductor substrate and connect adjacent resistive layers to each other, but not to the buried electrodes. Gate insulating layers may be formed on the channel regions of the semiconductor substrate. Gate electrodes may be formed on the gate insulating layers and extend over the resistive layers.

    摘要翻译: 提供了一种非易失性存储器件及其操作和制造方法,用于更高的集成度和更高的速度,同时允许较低的工作电流。 非易失性存储器件可以包括半导体衬底。 各自存储可变电阻状态的电阻层可以形成在半导体衬底的表面上。 掩埋电极可以形成在半导体衬底下的电阻层下,并且可以连接到电阻层。 通道区域可以形成在半导体衬底的表面上,并且将相邻的电阻层彼此连接,而不是埋入电极。 栅极绝缘层可以形成在半导体衬底的沟道区上。 栅电极可以形成在栅极绝缘层上并在电阻层上延伸。