公开(公告)号：US06541822B2

公开(公告)日：2003-04-01

申请号：US10039071

申请日：2002-01-02

Applicant: Geum-Jong Bae ,  Nae-In Lee ,  Hee-Sung Kang ,  Yun-Hee Lee

Inventor： Geum-Jong Bae ,  Nae-In Lee ,  Hee-Sung Kang ,  Yun-Hee Lee

IPC: H01L2120

CPC classification number: H01L29/78612 ,  H01L21/76283 ,  H01L27/1203

Abstract: A method of forming a SOI type semiconductor device comprises forming a first trench in a SOI layer forming a portion of an isolation layer region between an element region and a ground region by etching the SOI layer of a SOI type substrate using an etch stop layer pattern as an etch mask, forming an impurity layer in or on a bottom surface of the first trench, forming a second trench exposing a buried oxide layer in the SOI layer in the remainder of the isolation layer region except the portion thereof between the element region and the ground region, and forming an isolation layer by depositing an insulation layer over the SOI substrate having the first and second trenches. The impurity layer can be formed by depositing a SiGe single crystal layer in the bottom surface of the first trench. Also, the impurity layer can be formed by implanting ions in the bottom surface of the first trench.

Abstract translation: 一种形成SOI型半导体器件的方法包括：通过使用蚀刻停止层图案蚀刻SOI型衬底的SOI层，在形成元件区域和接地区域之间的隔离层区域的一部分的SOI层中形成第一沟槽 作为蚀刻掩模，在第一沟槽的底表面中或其上形成杂质层，形成第二沟槽，其在隔离层区域的其余部分中的SOI层内露出掩埋氧化物层，除了元件区域和 并且通过在具有第一沟槽和第二沟槽的SOI衬底上沉积绝缘层来形成隔离层。 可以通过在第一沟槽的底表面中沉积SiGe单晶层来形成杂质层。 此外，可以通过在第一沟槽的底表面中注入离子来形成杂质层。

公开(公告)号：US06476489B1

公开(公告)日：2002-11-05

申请号：US09258292

申请日：1999-02-26

Applicant: Bong-young Yoo ,  Dae-hong Ko ,  Nae-in Lee ,  Young-wook Park

Inventor： Bong-young Yoo ,  Dae-hong Ko ,  Nae-in Lee ,  Young-wook Park

IPC: H01L2348

CPC classification number: H01L23/485 ,  H01L21/28061 ,  H01L21/76805 ,  H01L23/5226 ,  H01L23/53271 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/4983 ,  H01L2924/0002 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908 ,  H01L2924/00

Abstract: A semiconductor device adopting an interlayer contact structure between upper and lower conductive layers and a method of manufacturing the semiconductor device adopting the structure are provided. The lower conductive layer includes a first conductive layer and a first silicide layer stacked together. The upper conductive layer includes a second conductive layer doped with impurities and a second silicide layer stacked together. In the interlayer contact structure, the first and second conductive layers are in direct contact with each other. This decreases the contact resistance between the two conductive layers and improves the electrical properties of the device.

Abstract translation: 提供了采用上下导电层之间的层间接触结构的半导体器件以及采用该结构制造半导体器件的方法。 下导电层包括堆叠在一起的第一导电层和第一硅化物层。 上导电层包括掺杂有杂质的第二导电层和堆叠在一起的第二硅化物层。 在层间接触结构中，第一和第二导电层彼此直接接触。 这降低了两个导电层之间的接触电阻并改善了器件的电性能。

公开(公告)号：US06239493B1

公开(公告)日：2001-05-29

申请号：US09258292

申请日：1999-02-26

Applicant: Bong-young Yoo ,  Dae-hong Ko ,  Nae-in Lee ,  Young-wook Park

Inventor： Bong-young Yoo ,  Dae-hong Ko ,  Nae-in Lee ,  Young-wook Park

IPC: H01L2348

Abstract: A semiconductor device adopting an interlayer contact structure between upper and lower conductive layers and a method of manufacturing the semiconductor device adopting the structure are provided. The lower conductive layer includes a first conductive layer and a first silicide layer stacked together. The upper conductive layer includes a second conductive layer doped with impurities and a second silicide layer stacked together. In the interlayer contact structure, the first and second conductive layers are in direct contact with each other. This decreases the contact resistance between the two conductive layers and improves the electrical properties of the device.

公开(公告)号：US09666478B2

公开(公告)日：2017-05-30

申请号：US15048993

申请日：2016-02-19

Applicant: Thomas Oszinda ,  Tae-Jin Yim ,  Sang-Hoon Ahn ,  Nae-In Lee

Inventor： Thomas Oszinda ,  Tae-Jin Yim ,  Sang-Hoon Ahn ,  Nae-In Lee

IPC: H01L21/76 ,  H01L21/768

CPC classification number: H01L21/76831 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2221/1047

Abstract: In a method of forming a wiring structure, an insulating interlayer is formed on a substrate. The insulating interlayer includes an opening and has pores distributed therein and exposed at a surface thereof. The insulating interlayer is exposed to a silane compound to form a pore sealing layer on the surface of the insulating interlayer and a sidewall of the opening. A conductive pattern filling the opening is formed on the pore sealing layer.

公开(公告)号：US20160307842A1

公开(公告)日：2016-10-20

申请号：US15006265

申请日：2016-01-26

Applicant: Jong-Min BAEK ,  Sang-Hoon AHN ,  Woo-Kyung YOU ,  Byung-Hee KIM ,  Young-Ju PARK ,  Nae-in LEE ,  Kyung-Min CHUNG

Inventor： Jong-Min BAEK ,  Sang-Hoon AHN ,  Woo-Kyung YOU ,  Byung-Hee KIM ,  Young-Ju PARK ,  Nae-in LEE ,  Kyung-Min CHUNG

IPC: H01L23/522 ,  H01L27/088 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823475

Abstract: A semiconductor device includes a plurality of wiring structures spaced apart from each other, and an insulating interlayer structure. Each of the wiring structures includes a metal pattern and a barrier pattern covering a sidewall, a bottom surface, and an edge portion of a top surface of the metal pattern and not covering a central portion of the top surface of the metal pattern. The insulating interlayer structure contains the wiring structures therein, and has an air gap between the wiring structures.

Abstract translation: 半导体器件包括彼此间隔开的多个布线结构和绝缘夹层结构。 每个布线结构包括金属图案和覆盖金属图案的顶表面的侧壁，底表面和边缘部分并且不覆盖金属图案的顶表面的中心部分的阻挡图案。 绝缘层间结构包含其中的布线结构，并且在布线结构之间具有气隙。

公开(公告)号：US09214530B2

公开(公告)日：2015-12-15

申请号：US14033639

申请日：2013-09-23

Applicant: Dong-Suk Shin ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

Inventor： Dong-Suk Shin ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/04 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

Abstract translation: 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成包含磷的快速蚀刻区域，并且通过使快速蚀刻区域凹陷来在有源区中形成第一沟槽。 所述方法还可以包括通过使用定向蚀刻工艺扩大第一沟槽并在第二沟槽中形成应力源来在有源区域中形成第二沟槽。 第二沟槽可以包括有源区的切口部分。

公开(公告)号：US20150287682A1

公开(公告)日：2015-10-08

申请号：US14637640

申请日：2015-03-04

Applicant: Sang Hoon AHN ,  Sangho RHA ,  Jongmin BAEK ,  Wookyung YOU ,  Nae-In LEE

Inventor： Sang Hoon AHN ,  Sangho RHA ,  Jongmin BAEK ,  Wookyung YOU ,  Nae-In LEE

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first conductive pattern on a substrate, an insulating diffusion barrier layer conformally covering a surface of the first conductive pattern, the insulation diffusion barrier layer exposed by an air gap region adjacent to a sidewall of the first conductive pattern, and a second conductive pattern on the first conductive pattern, the second conductive pattern penetrating the insulating diffusion barrier layer so as to be in contact with the first conductive pattern.

Abstract translation: 半导体器件包括：衬底上的第一导电图案，保形地覆盖第一导电图案的表面的绝缘扩散阻挡层，由邻近第一导电图案的侧壁的气隙区域暴露的绝缘扩散阻挡层，以及 第二导电图案在第一导电图案上，第二导电图案穿透绝缘扩散阻挡层，以便与第一导电图案接触。

公开(公告)号：US20150037980A1

公开(公告)日：2015-02-05

申请号：US14284674

申请日：2014-05-22

Applicant: Sangho Rha ,  Jongmin Baek ,  Wookyung You ,  Sanghoon Ahn ,  Nae-In Lee

Inventor： Sangho Rha ,  Jongmin Baek ,  Wookyung You ,  Sanghoon Ahn ,  Nae-In Lee

IPC: H01L21/306 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/02178 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/288 ,  H01L21/306 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

Abstract translation: 提供了形成半导体器件的方法。 形成半导体器件的方法可以包括在金属图案上和在绝缘层的相邻部分上形成覆盖层，所述覆盖层包括相对于绝缘层在金属图案上的第一蚀刻选择性，第二 在绝缘层的部分上相对于绝缘层的蚀刻选择性。 此外，该方法可以包括通过从绝缘层的部分去除覆盖层来形成与金属图案相邻的凹陷区域。 在从绝缘层的部分去除覆盖层之后，覆盖层的至少一部分可以保留在金属图案的最上表面上。 还提供了相关的半导体器件。

公开(公告)号：US20130320434A1

公开(公告)日：2013-12-05

申请号：US13908440

申请日：2013-06-03

Applicant: Dong-Suk Shin ,  Myung-Sun Kim ,  Seong-Jin Nam ,  Pan-Kwi Park ,  Hoi-Sung Chung ,  Nae-In Lee

Inventor： Dong-Suk Shin ,  Myung-Sun Kim ,  Seong-Jin Nam ,  Pan-Kwi Park ,  Hoi-Sung Chung ,  Nae-In Lee

IPC: H01L29/78

CPC classification number: H01L27/1104 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/28247 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/513 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7827 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: In a semiconductor device, a first active region has a first Σ-shape, and the second active region has a second Σ-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

Abstract translation: 在半导体器件中，第一有源区具有第一西格玛形状，第二有源区具有第二西格玛形状。 当垂直于衬底并将第一栅电极的侧表面通过第一区域的线被定义为第一垂直线时，当垂直于衬底并通过第二栅电极的侧表面的线 在第二区域被定义为第二垂直线时，当第一垂直线和第一沟槽之间的最短距离被定义为第一水平距离时，并且当第二垂直线和第二沟槽之间的最短距离被定义为 第二水平距离，第一水平距离和第二水平距离之间的差等于或小于1nm。

公开(公告)号：US08518723B2

公开(公告)日：2013-08-27

申请号：US12591534

申请日：2009-11-23

Applicant: Chong-Kwang Chang ,  Hong-Jae Shin ,  Nae-In Lee ,  Kwang-Hyeon Baik ,  Seung-Il Bok ,  Hyo-Jeong Kim

Inventor： Chong-Kwang Chang ,  Hong-Jae Shin ,  Nae-In Lee ,  Kwang-Hyeon Baik ,  Seung-Il Bok ,  Hyo-Jeong Kim

IPC: H01L21/302

CPC classification number: H01L21/0337

Abstract: A method of fabricating a semiconductor integrated circuit device, including providing a semiconductor substrate, sequentially forming an etching target layer and a hard mask layer on the semiconductor substrate, forming first etch masks on the hard mask layer, the first etch masks including a plurality of first line patterns spaced apart from one another at a first pitch and extending in a first direction, forming first hard mask patterns by etching the hard mask layer using the first etch masks, forming second etch masks on the first hard mask patterns, the second etch masks including a plurality of second line patterns spaced apart from one another at a second pitch and extending in a second direction different from the first direction, forming second hard mask patterns by etching the first hard mask patterns using the second etch masks, forming spacers on sidewalls of the second hard mask patterns, and patterning the etching target layer using the second hard mask patterns having the spacers.

Abstract translation: 一种制造半导体集成电路器件的方法，包括提供半导体衬底，在半导体衬底上依次形成蚀刻目标层和硬掩模层，在硬掩模层上形成第一蚀刻掩模，第一蚀刻掩模包括多个 第一线图案以第一间距彼此间隔开并且沿第一方向延伸，通过使用第一蚀刻掩模蚀刻硬掩模层来形成第一硬掩模图案，在第一硬掩模图案上形成第二蚀刻掩模，第二蚀刻 掩模，包括以第二间距彼此间隔开并且沿与第一方向不同的第二方向延伸的多个第二线图案，通过使用第二蚀刻掩模蚀刻第一硬掩模图案形成第二硬掩模图案，在第 第二硬掩模图案的侧壁，以及使用具有t的第二硬掩模图案来图案化蚀刻目标层 他的间隔。