METHOD TO PROVIDE A TIME-OF-FLIGHT ESTIMATE
    62.
    发明公开

    公开(公告)号:US20240201351A1

    公开(公告)日:2024-06-20

    申请号:US18532939

    申请日:2023-12-07

    CPC classification number: G01S7/52025

    Abstract: Method to provide a TOF estimate by a TOF device. The method comprises: generating an electric echo signal indicative of an ultrasonic echo signal returned by a target body by the ultrasonic source signal; determining an envelope signal indicative of an envelope of the electric echo signal; generating a first TOF estimate by processing the electric echo signal; determining an envelope signal portion of the envelope signal based on a non-PSOA hyperparameter; and generating a second TOF estimate by processing the envelope signal portion through PSOA, the second TOF estimate having a measurement accuracy value greater than that of the first TOF estimate. PSOA is optimized based on a PSOA hyperparameter set. The non-PSOA hyperparameter and the PSOA hyperparameter set are selected among a plurality of choices based on the first TOF estimate, so as to obtain the second TOF estimate which has greater accuracy than the first TOF estimate.

    PROCESS FOR MANUFACTURING A MICRO-ELECTRO-MECHANICAL DEVICE, AND MEMS DEVICE

    公开(公告)号:US20240199408A1

    公开(公告)日:2024-06-20

    申请号:US18590533

    申请日:2024-02-28

    Abstract: A process for manufacturing a MEMS device includes forming a first structural layer of a first thickness on a substrate. First trenches are formed through the first structural layer, and masking regions separated by first openings are formed on the first structural layer. A second structural layer of a second thickness is formed on the first structural layer in direct contact with the first structural layer at the first openings and forms, together with the first structural layer, thick structural regions having a third thickness equal to the sum of the first and the second thicknesses. A plurality of second trenches are formed through the second structural layer, over the masking regions, and third trenches are formed through the first and the second structural layers by removing selective portions of the thick structural regions.

    Control loop and efficiency enhancement for DC-DC converters

    公开(公告)号:US12015346B2

    公开(公告)日:2024-06-18

    申请号:US17565674

    申请日:2021-12-30

    CPC classification number: H02M3/158 H02M1/0025 H02M1/08

    Abstract: A DC-DC boost converter includes an inductor coupled between an input voltage and an input node, a diode coupled between the input node and an output node, and an output capacitor coupled between the output node and ground such that an output voltage is formed across the output capacitor. A switch selectively couples the input node to ground in response to a drive signal. Control loop circuitry includes an error amplifier to generate an analog error voltage based upon a comparison of a feedback voltage to a reference voltage, the feedback voltage being indicative of the output voltage, a quantizer to quantize the analog error voltage to produce a digital error signal, and a drive voltage generation circuit to generate the drive signal as having a duty cycle based upon the digital error signal.

    Noise shaper variable quantizer
    67.
    发明授权

    公开(公告)号:US12003247B2

    公开(公告)日:2024-06-04

    申请号:US17846520

    申请日:2022-06-22

    CPC classification number: H03M1/0668 H03M1/0626 H03M1/0648 H03M3/492 H03M3/51

    Abstract: A signal processing circuit includes a filter generating a quantizer input signal from a noise shaping input signal and a quantizer output signal. A quantizer divides the quantizer input signal by a scaling factor to produce a noise shaping output signal and multiplies the noise shaping output signal by the scaling factor to produce the quantizer output signal. Receiver circuitry scales the quantizer output signal by a second scaling factor. A dynamic range optimization circuit compares a current value of the noise shaping input signal to a threshold value, lowers or raises the scaling factor in response to the comparison, and proportionally lowers or raises the scaling factor such that a ratio between the scaling factor and second scaling factor remains substantially constant.

    Semiconductor device and corresponding method

    公开(公告)号:US11990442B2

    公开(公告)日:2024-05-21

    申请号:US17537112

    申请日:2021-11-29

    Abstract: A semiconductor die is mounted at a die area of a ball grid array package that includes an array of electrically-conductive ball. A power channel conveys a power supply current to the semiconductor die. The power channel is formed by an electrically-conductive connection plane layers extending in a longitudinal direction between a distal end at a periphery of the package and a proximal end at the die area. A distribution of said electrically-conductive balls is made along the longitudinal direction. The electrically-conductive connection plane layer includes subsequent portions in the longitudinal direction between adjacent electrically-conductive balls of the distribution. Respective electrical resistance values of the subsequent portions monotonously decrease from the distal end to the proximal end. A uniform distribution of power supply current over the length of the power channel is thus facilitated.

Patent Agency Ranking