公开(公告)号：US20120243314A1

公开(公告)日：2012-09-27

申请号：US13301948

申请日：2011-11-22

Applicant: Takashi MAEDA

Inventor： Takashi MAEDA

IPC: G11C16/04 ,  H01L29/792

CPC classification number: H01L27/11582 ,  H01L27/11565

Abstract: A nonvolatile semiconductor memory device according to one aspect includes a semiconductor substrate, a memory string, a plurality of first conductive layers, a second conductive layer, and a third conductive layer. The memory string has a plurality of memory cells, a dummy transistor and a back gate transistor connected in series in a direction perpendicular to the semiconductor substrate. The plurality of first conductive layers are electrically connected to gates of the memory cells. The second conductive layer is electrically connected to a gate of the dummy transistor. The third conductive layer is electrically connected to a gate of the back gate transistor. The second conductive layer is short-circuited with the third conductive layer.

Abstract translation: 根据一个方面的非易失性半导体存储器件包括半导体衬底，存储器串，多个第一导电层，第二导电层和第三导电层。 存储器串具有与垂直于半导体衬底的方向串联连接的多个存储单元，虚拟晶体管和背栅晶体管。 多个第一导电层电连接到存储单元的栅极。 第二导电层电连接到虚拟晶体管的栅极。 第三导电层电连接到背栅晶体管的栅极。 第二导电层与第三导电层短路。

公开(公告)号：US20120176836A1

公开(公告)日：2012-07-12

申请号：US13091589

申请日：2011-04-21

Applicant: Natsuki IGUCHI ,  Takashi MAEDA

Inventor： Natsuki IGUCHI ,  Takashi MAEDA

IPC: G11C16/28 ,  G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/10 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

Abstract: According to one embodiment, a non-volatile semiconductor memory device comprises memory strings. Each memory string comprises a semiconductor layer, control gates, a first selection gate, and a second selection gate. A semiconductor layer comprises a pair of pillar portions which extend in a vertical direction to a substrate, and a coupling portion formed to couple the pair of pillar portions. Control gates orthogonally intersect one of the pair of pillar portions or the other of the pair of pillar portions. A first selection gate orthogonally intersects one of the pair of pillar portions and is formed above the control gates. A second selection gate orthogonally intersects the other of the pair of pillar portions, is formed above the control gates, and is on the same level as the first selection gate as well as integrated with the first selection gate.

Abstract translation: 根据一个实施例，非易失性半导体存储器件包括存储器串。 每个存储器串包括半导体层，控制栅极，第一选择栅极和第二选择栅极。 半导体层包括在垂直方向上延伸到基板的一对柱部分和形成为耦合所述一对柱部分的联接部分。 控制栅极与一对柱部分中的一个或一对柱部分中的另一个正交相交。 第一选择栅极与一对柱部分中的一个正交相交并形成在控制栅极的上方。 与控制栅极之间形成与第一选择栅极相同的第二选择栅极，与第一选择栅极集成，与第一选择栅极成一体。

公开(公告)号：US20100310410A1

公开(公告)日：2010-12-09

申请号：US12815527

申请日：2010-06-15

Applicant: Satoshi Matsumoto ,  Keisuke Nagashima ,  Takashi Maeda

Inventor： Satoshi Matsumoto ,  Keisuke Nagashima ,  Takashi Maeda

IPC: C22C14/00

CPC classification number: C22C14/00 ,  C22F1/183

Abstract: There is provided a titanium alloy for corrosion-resistant materials, which contains 0.01-0.12% by mass in total of at least one of platinum group elements; at least Si and one of, or both of, Sn and Mn, selected from the group consisting of Al, Cr, Zr, Nb, Si, Sn and Mn, wherein the total content of Al, Cr, Zr, Nb, Si, Sn and Mn is 5% by mass or less; and the residue comprising Ti and impurities.

Abstract translation: 提供了一种用于耐腐蚀材料的钛合金，其总共含有0.01〜0.12质量％的铂族元素中的至少一种; 选自Al，Cr，Zr，Nb，Si，Sn和Mn中的至少一种Si和Sn和Mn中的一种或两种，其中Al，Cr，Zr，Nb，Si， Sn和Mn为5质量％以下， 并且残余物包含Ti和杂质。

公开(公告)号：US20100214838A1

公开(公告)日：2010-08-26

申请号：US12694690

申请日：2010-01-27

Applicant: TOMOO HISHIDA ,  YOSHIHISA IWATA ,  KIYOTARO ITAGAKI ,  TAKASHI MAEDA

Inventor： TOMOO HISHIDA ,  YOSHIHISA IWATA ,  KIYOTARO ITAGAKI ,  TAKASHI MAEDA

IPC: G11C16/04 ,  G11C11/34

CPC classification number: G11C8/08 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/3454 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582

Abstract: A non-volatile semiconductor storage device includes a control circuit performing an erase operation to erase data from a selected one of memory transistors. The control circuit applies a first voltage to the other end of selected one of selection transistors, causes the selected one of the selection transistors to turn on, and causes any one of the memory transistors to turn on that is closer to the selection transistor than the selected one of the memory transistors. The control circuit also applies a second voltage lower than the first voltage to a gate of the selected one of the memory transistors. Such a potential difference between the first voltage and the second voltage causing a change in electric charges in the electric charge storage layer.

Abstract translation: 非挥发性半导体存储装置包括执行擦除操作以从存储晶体管中选定的一个擦除数据的控制电路。 控制电路向所选择的一个选择晶体管的另一端施加第一电压，使所选择的一个选择晶体管导通，并且使存储晶体管中的任何一个导通比接近选择晶体管更接近选择晶体管 选择一个存储晶体管。 控制电路还将低于第一电压的第二电压施加到所选存储晶体管的栅极。 第一电压和第二电压之间的这种电位差导致电荷存储层中的电荷变化。

公开(公告)号：US20100172189A1

公开(公告)日：2010-07-08

申请号：US12620986

申请日：2009-11-18

Applicant: Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Akihiro Nitayama ,  Takashi Maeda ,  Tomoo Hishida

Inventor： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Akihiro Nitayama ,  Takashi Maeda ,  Tomoo Hishida

IPC: G11C16/04 ,  G11C7/06

CPC classification number: G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30

Abstract: A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.

Abstract translation: 非易失性半导体存储装置包括：包括串联连接的多个存储单元的存储串; 第一选择晶体管，其一端连接到存储器串的一端; 第一布线，其一端连接到第一选择晶体管的另一端; 连接到第一选择晶体管的栅极的第二布线。 控制电路被配置为在保持第一布线的电压大于第二布线的电压一定电位差的同时，在擦除操作中提高第二布线和第一布线的电压。 一定的电位差是导致GIDL电流的电位差。

公开(公告)号：US20090242968A1

公开(公告)日：2009-10-01

申请号：US12408183

申请日：2009-03-20

Applicant: Takashi MAEDA ,  Yoshihisa Iwata

Inventor： Takashi MAEDA ,  Yoshihisa Iwata

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.

Abstract translation: 在非易失性半导体存储器件中，通过在硅衬底上交替堆叠电介质膜和导电膜来形成层叠体，并且以矩阵形式形成沿堆叠方向延伸的多个通孔。 分路互连和位互连设置在堆叠体的上方。 导体支柱埋设在多个通孔中的分流互连的正下方配置的贯通孔的内侧，半导体柱埋设在剩余通孔的内部。 导电柱由金属或低电阻硅形成。 其上端部连接到分路互连，并且其下端部连接到形成在硅衬底的上层部分中的电池源。

公开(公告)号：US07388214B2

公开(公告)日：2008-06-17

申请号：US11315303

申请日：2005-12-23

Applicant: Takashi Maeda

Inventor： Takashi Maeda

IPC: G21K5/04

CPC classification number: H01J37/3177 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/243 ,  H01J37/304 ,  H01J2237/0453 ,  H01J2237/30472

Abstract: A charged particle beam exposure apparatus which splits a charged-particle beam from a charged-particle beam source into a plurality of charged-particle beams by a plurality of apertures formed in an aperture array to expose a wafer using the plurality of charged-particle beams. The apparatus includes a stage on which the wafer is loaded, the wafer being irradiated with the plurality of charged-particle beams, which have been passed through the apertures of the aperture array, a plurality of detection electrodes which detect intensities of the plurality of charged-particle beams passing through the plurality of apertures of the aperture array to expose the wafer with the plurality of charged-particle beams, the plurality of detection electrodes being formed on the charged-particle beam source side of the light-shielding peripheral regions of the plurality of apertures of the aperture array, and a grid array which adjusts the intensities of the plurality of charged-particle beams on the basis of detection results obtained by the plurality of detection electrodes.

Abstract translation: 一种带电粒子束曝光装置，其通过形成在孔径阵列中的多个孔将带电粒子束从带电粒子束源分解成多个带电粒子束，以使用多个带电粒子束 。 该装置包括载置晶片的阶段，已经通过孔径阵列的孔径的多个带电粒子束照射的晶片，多个检测电极，其检测多个带电粒子的强度 粒子束通过孔径阵列的多个孔径以暴露具有多个带电粒子束的晶片，所述多个检测电极形成在所述光屏蔽外围区域的带电粒子束源侧上 孔阵列的多个孔，以及基于由多个检测电极获得的检测结果来调整多个带电粒子束的强度的栅格阵列。

公开(公告)号：US07214646B1

公开(公告)日：2007-05-08

申请号：US10048470

申请日：2000-08-09

Applicant: Takeshi Fujino ,  Shigeki Oyama ,  Naohiko Oki ,  Minoru Noguchi ,  Kenji Sato ,  Shushi Nishimura ,  Takashi Maeda ,  Yuji Kawabuchi ,  Takahiro Haga

Inventor： Takeshi Fujino ,  Shigeki Oyama ,  Naohiko Oki ,  Minoru Noguchi ,  Kenji Sato ,  Shushi Nishimura ,  Takashi Maeda ,  Yuji Kawabuchi ,  Takahiro Haga

IPC: C01B31/08

CPC classification number: H01G9/155 ,  H01G11/34 ,  H01G11/58 ,  Y02E60/13

Abstract: To produce activated carbon for an electrode of an electric double-layer capacitor, the following steps are carried out sequentially: a step of subjecting a massive mesophase pitch to a pulverizing treatment to provide a pulverized powder; a step of subjecting the pulverized powder to an infusibilizing treatment under conditions of a temperature in a range of 300° C. (inclusive) to 450° C. (inclusive) in the atmospheric air current, a step of subjecting the pulverized powder to a carbonizing treatment under conditions of a temperature in a range of 600° C. (inclusive) to 900° C. (inclusive) in an inert gas current to provide a carbonized powder, a step of subjecting the carbonized powder to an alkali activating treatment under conditions of a temperature in a range of 500° C. (inclusive) to 1,000° C. (inclusive) in an inert gas atmosphere, followed by the post treatments, thereby producing alkali-activated carbon, and a step of subjecting the alkali-activated carbon to a pulverizing treatment. If an electrode is produced using the activated carbon, the electrode density can be increased.

Abstract translation: 为了制造双电层电容器的电极用活性炭，依次进行以下步骤：将大量的中间相沥青进行粉碎处理以提供粉碎粉末的步骤; 在大气气流中，在温度范围为300℃〜450℃的条件下对粉碎粉进行渗透处理的工序，将粉碎粉末 在惰性气流中在600℃（含）〜900℃（以下）的温度条件下进行碳化处理，得到碳化粉末，将碳化粉末进行碱活化处理的工序 在惰性气体气氛中，在500℃（含）-100℃（含）范围内的温度条件进行后处理，从而制造碱活性炭， 活性炭进行粉碎处理。 如果使用活性炭制造电极，则可以提高电极密度。

公开(公告)号：US07212902B2

公开(公告)日：2007-05-01

申请号：US11030401

申请日：2005-01-07

Applicant: Hiroshi Fujioka ,  Takanori Matsunaga ,  Takashi Maeda ,  Toshinori Matsui ,  Masahiko Kurishige ,  Hideyuki Tanaka

Inventor： Hiroshi Fujioka ,  Takanori Matsunaga ,  Takashi Maeda ,  Toshinori Matsui ,  Masahiko Kurishige ,  Hideyuki Tanaka

IPC: G06F7/00

CPC classification number: B62D6/005 ,  B60T2230/02 ,  B60T2260/02 ,  B62D6/04

Abstract: System for detecting stability/instability of behavior of a motor vehicle upon occurrence of tire slip or lock. State of the motor vehicle is determined on the basis of an alignment torque (Ta) applied from a road and a side slip angle (β). By taking advantage of such torque/slip-angle characteristic that although the alignment torque is proportional to a side slip angle when the latter is small, the alignment torque becomes smaller as the side slip angle increases, a normal value is determined from a straight line slope and the side slip angle in a region where the latter is small. Unstable behavior of the motor vehicle is determined when deviation of actual measured value from the normal value increases. Further, unstable state is determined when the slope of the alignment torque for the slip angle departs significantly from that of approximate straight line slope.

Abstract translation: 用于在发生轮胎滑动或锁定时检测机动车辆的行为的稳定性/不稳定性的系统。 基于从道路施加的对准扭矩（Ta）和侧滑角（β）来确定机动车辆的状态。 通过利用这样的扭矩/滑移角特性，即使在后者较小时，对位转矩与侧滑角成比例，随着侧滑角增大，对位转矩变小，从直线 斜率和侧滑角在后者较小的区域。 当实际测量值与正常值的偏差增加时，确定机动车辆的不稳定行为。 此外，当滑移角的对准扭矩的斜率与近似直线斜率的斜率大大偏离时，确定不稳定状态。

公开(公告)号：US20060174045A1

公开(公告)日：2006-08-03

申请号：US11332370

申请日：2006-01-17

Applicant: Takashi Maeda ,  Mamoru Sumida ,  Takuji Kioka

Inventor： Takashi Maeda ,  Mamoru Sumida ,  Takuji Kioka

IPC: G06F13/36 ,  G06F12/14

CPC classification number: G06F13/364 ,  G06F12/0802

Abstract: An access priority in bus arbitration is changed based on a cache hit ratio so as to perform the bus arbitration. In order to perform the bus arbitration, a cache hit ratio measuring device investigates a status of a cache access by a bus master. A bus arbitration managing device changes a priority in a priority storing device based on an information outputted from the cache hit ratio measuring device. Then, a bus arbitration device performs the bus arbitration in accordance with the priority.

Abstract translation: 总线仲裁中的访问优先级基于高速缓存命中率而改变，以便执行总线仲裁。 为了执行总线仲裁，缓存命中率测量装置调查总线主控器的高速缓存访​​问状态。 总线仲裁管理装置基于从高速缓存命中率测量装置输出的信息来改变优先级存储装置中的优先级。 然后，总线仲裁装置根据优先级执行总线仲裁。