公开(公告)号：US07652322B2

公开(公告)日：2010-01-26

申请号：US12014262

申请日：2008-01-15

Applicant: Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

Inventor： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

IPC: H01L29/788

CPC classification number: H01L29/66825 ,  H01L29/42324 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

Abstract: In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.

Abstract translation: 在能够在控制栅极和存储节点（浮动栅极）之间保持增强的电场并且具有减小的单元尺寸的闪存器件以及制造闪存器件的方法中，闪速存储器件包括半导体衬底 具有一对漏极区域和形成在所述一对漏极区域之间的源极区域，每个形成在所述源极区域和每个所述漏极区域之间的所述半导体衬底上的一对间隔物形状的控制栅极，以及形成在所述漏极区域中的存储节点 控制栅极和半导体衬底之间的区域。 每个控制栅极的底表面包括与半导体衬底重叠的第一区域和与存储节点重叠的第二区域。 一对间隔物控制栅极围绕源极区域彼此大致对称。

公开(公告)号：US07601592B2

公开(公告)日：2009-10-13

申请号：US12135295

申请日：2008-06-09

Applicant: Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

Inventor： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L29/80

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L29/78645

Abstract: According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability.

Abstract translation: 根据本发明的具有多栅极结构的非易失性存储器件及其形成方法，使用镶嵌工艺形成栅电极。 因此，在用于形成栅电极的工艺中，电荷存储层，隧道绝缘层，阻挡绝缘层和栅极电极层不会被蚀刻侵蚀，从而形成具有良好可靠性的非易失性存储器件。

公开(公告)号：US07439574B2

公开(公告)日：2008-10-21

申请号：US10460673

申请日：2003-06-13

Applicant: Chung-woo Kim ,  Byung-gook Park ,  Jong-duk Lee ,  Yong-kyu Lee

Inventor： Chung-woo Kim ,  Byung-gook Park ,  Jong-duk Lee ,  Yong-kyu Lee

IPC: H01L21/336

CPC classification number: H01L29/7926 ,  G11C11/5628 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7923

Abstract: Provided are a silicon/oxide/nitride/oxide/silicon (SONOS) memory, a fabricating method thereof, and a memory programming method. The SONOS memory includes a substrate; a first insulating layer stacked on the substrate; a semiconductor layer, which is patterned on the first insulating layer in a predetermined shape, including source and drain electrodes separated by a predetermined interval; a second insulating layer located on the semiconductor layer between the source and drain electrodes; a memory layer, which is deposited on sides of a portion of the semiconductor layer between the source and drain electrodes and on sides and an upper surface of the second insulating layer, including electron transferring channels and an electron storing layer; and a gate electrode, which is deposited on a surface of the memory layer, for controlling transfer of electrons in the memory layer. The programming method may provide a large capacity, stable, multi-level memory.

Abstract translation: 提供了硅/氧化物/氮化物/氧化物/硅（SONOS）存储器，其制造方法和存储器编程方法。 SONOS存储器包括基板; 堆叠在所述基板上的第一绝缘层; 半导体层，其在预定形状的第一绝缘层上图案化，包括以预定间隔隔开的源极和漏极; 位于源极和漏极之间的半导体层上的第二绝缘层; 存储层，其沉积在源极和漏极之间的半导体层的一部分的侧面上，并且沉积在包括电子传输沟道和电子存储层的第二绝缘层的侧面和上表面上; 以及沉积在存储层的表面上用于控制存储层中电子转移的栅电极。 编程方法可以提供大容量，稳定的多级存储器。

公开(公告)号：US07161206B2

公开(公告)日：2007-01-09

申请号：US11007760

申请日：2004-12-08

Applicant: Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

Inventor： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

IPC: H02L29/788 ,  H01L21/336

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L29/78645

Abstract: According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability.

Abstract translation: 根据本发明的具有多栅极结构的非易失性存储器件及其形成方法，使用镶嵌工艺形成栅电极。 因此，在用于形成栅电极的工艺中，电荷存储层，隧道绝缘层，阻挡绝缘层和栅极电极层不会被蚀刻侵蚀，从而形成具有良好可靠性的非易失性存储器件。

公开(公告)号：US20060086953A1

公开(公告)日：2006-04-27

申请号：US11296397

申请日：2005-12-08

Applicant: Yong-kyu Lee ,  Jeong-uk Han ,  Sung-taeg Kang ,  Jong-duk Lee ,  Byung-gook Park

Inventor： Yong-kyu Lee ,  Jeong-uk Han ,  Sung-taeg Kang ,  Jong-duk Lee ,  Byung-gook Park

IPC: H01L29/76 ,  H01L29/745

CPC classification number: H01L21/28282 ,  H01L29/66833 ,  H01L29/7923

Abstract: A twin-ONO-type SONOS memory includes a semiconductor substrate having a source region, a drain region and a channel region between the source and drain regions, twin silicon oxide-silicon nitride-silicon oxide (ONO) dielectric layers, a first ONO dielectric layer being on the channel region and the source region and as second ONO dielectric layer being on the channel region and the drain region, and a control gate on the channel region, between the twin ONO dielectric layers, the twin ONO dielectric layers extending along at least lower lateral sides of the control gate adjacent the channel region, wherein the twin ONO dielectric layers extend towards the source and drain regions further than the control gate.

公开(公告)号：US20050272192A1

公开(公告)日：2005-12-08

申请号：US11020899

申请日：2004-12-23

Applicant: Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

Inventor： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/786

CPC classification number: H01L29/7854 ,  B82Y10/00 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/78645

Abstract: A method of forming a fin field effect transistor on a semiconductor substrate includes forming a fin-shaped active region vertically protruding from the substrate. An oxide layer is formed on a top surface and opposing sidewalls of the fin-shaped active region. An oxidation barrier layer is formed on the opposing sidewalls of the fin-shaped active region and is planarized to a height no greater than about a height of the oxide layer to form a fin structure. The fin structure is oxidized to form a capping oxide layer on the top surface of the fin-shaped active region and to form at least one curved sidewall portion proximate the top surface of the fin-shaped active region. The oxidation barrier layer has a height sufficient to reduce oxidation on the sidewalls of the fin-shaped active region about halfway between the top surface and a base of the fin-shaped active region. Related devices are also discussed.

Abstract translation: 在半导体衬底上形成鳍状场效应晶体管的方法包括形成从衬底垂直突出的鳍状有源区。 在鳍状有源区的上表面和相对侧壁上形成氧化物层。 在翅片状有源区域的相对的侧壁上形成氧化阻挡层，并将其平坦化至不大于氧化物层高度的高度以形成翅片结构。 翅片结构被氧化以在翅片形有源区的顶表面上形成封盖氧化层，并且在翅片形有源区的顶表面附近形成至少一个弯曲的侧壁部分。 氧化阻挡层的高度足以减小翅片形有源区的侧壁上的氧化，大约在鳍状有源区的顶表面和基底之间的一半处。 还讨论了相关设备。

公开(公告)号：US20050227435A1

公开(公告)日：2005-10-13

申请号：US11007760

申请日：2004-12-08

Applicant: Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

Inventor： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

IPC: H01L21/336 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L29/78645

Abstract: According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability.

Abstract translation: 根据本发明的具有多栅极结构的非易失性存储器件及其形成方法，使用镶嵌工艺形成栅电极。 因此，在用于形成栅电极的工艺中，电荷存储层，隧道绝缘层，阻挡绝缘层和栅极电极层不会被蚀刻侵蚀，从而形成具有良好可靠性的非易失性存储器件。

公开(公告)号：US10453801B2

公开(公告)日：2019-10-22

申请号：US15093006

申请日：2016-04-07

Applicant: Bo-young Seo ,  Yong-kyu Lee

Inventor： Bo-young Seo ,  Yong-kyu Lee

IPC: H01L43/08 ,  H01L23/552 ,  G11C11/16 ,  H01L23/00 ,  H01L25/065 ,  H01L27/22

Abstract: A magnetic random-access memory (MRAM) device and a semiconductor package include a magnetic shielding layer that may suppress at least one of magnetic orientation errors and deterioration of magnetic tunnel junction (MTJ) structures due to external magnetic fields. A semiconductor device includes: a MRAM chip including a MRAM; and a magnetic shielding layer including an upper shielding layer and a via shielding layer. The upper shielding layer is on a top surface of the MRAM chip, and the via shielding layer extends from the upper shielding layer and passes through the MRAM chip.

公开(公告)号：US09928892B2

公开(公告)日：2018-03-27

申请号：US15153866

申请日：2016-05-13

Applicant: Bo-young Seo ,  Yong-seok Chung ,  Gwan-hyeob Koh ,  Yong-kyu Lee

Inventor： Bo-young Seo ,  Yong-seok Chung ,  Gwan-hyeob Koh ,  Yong-kyu Lee

IPC: G11C11/00 ,  G11C11/16 ,  H01L43/08 ,  H01L27/22

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  H01L27/228 ,  H01L43/08

Abstract: A resistive memory apparatus includes a memory cell array having a plurality of memory cells and a first ground switch. The plurality of memory cells are arranged in a plurality of rows and a plurality of columns, and each memory cell in a first column of the plurality of memory cells is connected between a first bitline and a first source line. The first ground switch is connected in parallel with the first source line, and the first ground switch is configured to selectively provide a first current path from the first bitline to ground through a selected memory cell in the first column of the plurality of memory cells and the first source line, the current path traversing only a portion of the first source line.

公开(公告)号：US20170062032A1

公开(公告)日：2017-03-02

申请号：US15249845

申请日：2016-08-29

Applicant: Bo-young Seo ,  Suk-soo Pyo ,  Gwan-hyeob Koh ,  Yong-kyu Lee ,  Dae-shik kim

Inventor： Bo-young Seo ,  Suk-soo Pyo ,  Gwan-hyeob Koh ,  Yong-kyu Lee ,  Dae-shik kim

IPC: G11C11/16

CPC classification number: G11C11/161 ,  G11C7/14 ,  G11C11/1673 ,  G11C13/004 ,  G11C29/028 ,  G11C29/50008 ,  G11C2013/0054 ,  G11C2029/4402

Abstract: A semiconductor memory device includes a shorted variable resistor element in a memory cell. The semiconductor memory device includes main cells and reference cells each including a cell transistor and a variable resistor element. The variable resistor element of the reference cell is shorted by applying a breakdown voltage of a magnetic tunnel junction (MTJ) element, connection in parallel to a conductive via element, connection to a reference bit line at a node between the cell transistor and the variable resistor element, or replacement of the variable resistor element with the conductive via element. A sense amplifier increases a sensing margin of the main cell by detecting and amplifying a current flowing in a bit line of the main cell and a current flowing in the reference bit line to which a reference resistor is connected.

Abstract translation: 半导体存储器件包括存储单元中的短路可变电阻元件。 半导体存储器件包括主单元和参考单元，每个单元包括单元晶体管和可变电阻元件。 参考单元的可变电阻器元件通过施加磁性隧道结（MTJ）元件的击穿电压，与导电通孔元件并联的连接来短路，连接到单元晶体管和可变电极之间的节点处的参考位线 电阻元件或用导电通孔元件替换可变电阻元件。 感测放大器通过检测和放大在主单元的位线中流动的电流和在参考电阻器连接到的参考位线中流动的电流来增加主单元的感测容限。