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    MEMORY DEVICE WITH INTERNAL SIGNAL PROCESSING UNIT
    61.
    发明申请
    MEMORY DEVICE WITH INTERNAL SIGNAL PROCESSING UNIT 审中-公开
    具有内部信号处理单元的存储器件

    公开(公告)号：US20140298139A1

    公开(公告)日：2014-10-02

    申请号：US14306764

    申请日：2014-06-17

    Applicant: Apple Inc.

    Inventor： Dotan Sokolov ,  Naftali Sommer ,  Uri Perlmutter ,  Ofir Shalvi

    IPC: G06F11/10

    CPC classification number: G06F11/1072 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1076 ,  G06F12/00 ,  G11C11/56 ,  G11C29/50004 ,  G11C29/52 ,  G11C2029/5004

    Abstract: A method for operating a memory includes storing data in a plurality of analog memory cells that are fabricated on a first semiconductor die by writing input storage values to a group of the analog memory cells. After storing the data, multiple output storage values are read from each of the analog memory cells in the group using respective, different threshold sets of read thresholds, thus providing multiple output sets of the output storage values corresponding respectively to the threshold sets. The multiple output sets of the output storage values are preprocessed by circuitry that is fabricated on the first semiconductor die, to produce preprocessed data. The preprocessed data is provided to a memory controller, which is fabricated on a second semiconductor die that is different from the first semiconductor die. so as to enable the memory controller to reconstruct the data responsively to the preprocessed data.

    Abstract translation: 一种用于操作存储器的方法包括：通过将输入存储值写入到一组模拟存储器单元中，将数据存储在制造在第一半导体管芯上的多个模拟存储器单元中。 在存储数据之后，使用相应的不同的阈值集合读取组中每个模拟存储器单元的多个输出存储值，从而提供分别对应于阈值集合的输出存储值的多个输出组。 输出存储值的多个输出组由在第一半导体管芯上制造的电路预处理，以产生预处理的数据。 预处理数据被提供给存储器控制器，该存储器控制器制造在与第一半导体管芯不同的第二半导体管芯上。 以使得存储器控制器能够响应于预处理的数据重构数据。

    High-performance ECC decoder
    62.
    发明授权
    High-performance ECC decoder 有权
    高性能ECC解码器

    公开(公告)号：US08700977B2

    公开(公告)日：2014-04-15

    申请号：US13920140

    申请日：2013-06-18

    Applicant: Apple Inc.

    Inventor： Micha Anholt ,  Naftali Sommer ,  Gil Semo ,  Tal Inbar

    IPC: H03M13/00

    CPC classification number: G06F11/1076 ,  H03M13/03 ,  H03M13/1525 ,  H03M13/45 ,  H03M13/617

    Abstract: Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.

    Abstract translation: 用于纠错码（ECC）解码的方法包括从表示已经用ECC编码的数据的一组位产生综合征。 错误定位器多项式（ELP）是基于综合征产生的。 识别至少一些ELP根，并校正由这些根指示的错误。 可以通过应用向量空间中的比特向量操作来产生每个综合征。 通过使用向量空间的不同基础应用向量运算来产生每个综合征。 可以通过使用串行乘法器对ELP系数进行操作，在给定的场元件上评估ELP，其中每个串行乘法器执行乘法周期序列，并在每个周期中产生中间结果。 响应于检测至少一个中期结果，指示给定的元素不是ELP根，在完成序列之前终止乘法循环。

    Memory Device Readout Using Multiple Sense Times
    63.
    发明申请
    Memory Device Readout Using Multiple Sense Times 有权
    使用多重检测时间的存储器件读数

    公开(公告)号：US20130297989A1

    公开(公告)日：2013-11-07

    申请号：US13936622

    申请日：2013-07-08

    Applicant: Apple Inc.

    Inventor： Avraham Poza Meir ,  Barak Baum ,  Naftali Sommer

    IPC: G06F11/10

    CPC classification number: G06F11/1008 ,  G11C7/06 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4091 ,  G11C11/5642 ,  G11C13/004 ,  G11C13/0061 ,  G11C16/26 ,  G11C16/349 ,  G11C27/005 ,  G11C29/00 ,  G11C29/021 ,  G11C29/028 ,  G11C2211/5641

    Abstract: A method for data storage includes storing data in a group of analog memory cells by writing respective storage values into the memory cells in the group. One or more of the memory cells in the group are read using a first readout operation that senses the memory cells with a first sense time. At least one of the memory cells in the group is read using a second readout operation that senses the memory cells with a second sense time, longer than the first sense time. The data stored in the group of memory cells is reconstructed based on readout results of the first and second readout operations.

    Abstract translation: 用于数据存储的方法包括通过将相应的存储值写入组中的存储器单元来将数据存储在一组模拟存储器单元中。 使用以第一感测时间感测存储器单元的第一读出操作读取组中的一个或多个存储器单元。 使用第二读出操作来读取组中的至少一个存储器单元，该第二读出操作以比第一感测时间长的第二感测时间感测存储器单元。 基于第一和第二读出操作的读出结果重建存储在存储单元组中的数据。

    High-performance ECC decoder
    66.
    发明授权
    High-performance ECC decoder 有权
    高性能ECC解码器

    公开(公告)号：US09535788B2

    公开(公告)日：2017-01-03

    申请号：US14821124

    申请日：2015-08-07

    Applicant: Apple Inc.

    Inventor： Micha Anholt ,  Naftali Sommer ,  Gil Semo ,  Tal Inbar

    IPC: G06F11/10 ,  H03M13/45 ,  H03M13/00 ,  H03M13/15 ,  H03M13/03

    CPC classification number: G06F11/1076 ,  H03M13/03 ,  H03M13/1525 ,  H03M13/45 ,  H03M13/617

    Abstract: Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.

    Abstract translation: 用于纠错码（ECC）解码的方法包括从表示已经用ECC编码的数据的一组位产生综合征。 错误定位器多项式（ELP）是基于综合征产生的。 识别至少一些ELP根，并校正由这些根指示的错误。 可以通过应用向量空间中的比特向量操作来产生每个综合征。 通过使用向量空间的不同基础应用向量运算来产生每个综合征。 可以通过使用串行乘法器对ELP系数进行操作，在给定的场元件上评估ELP，其中每个串行乘法器执行乘法周期序列，并在每个周期中产生中间结果。 响应于检测至少一个中期结果，指示给定的元素不是ELP根，在完成序列之前终止乘法循环。

    Positioning Techniques for Narrowband Wireless Signals Under Dense Multipath Conditions
    67.
    发明申请
    Positioning Techniques for Narrowband Wireless Signals Under Dense Multipath Conditions 有权
    在密集多径条件下窄带无线信号的定位技术

    公开(公告)号：US20160381504A1

    公开(公告)日：2016-12-29

    申请号：US14749552

    申请日：2015-06-24

    Applicant: Apple Inc.

    Inventor： Naftali Sommer

    IPC: H04W4/02 ,  H04W4/00

    CPC classification number: H04W4/023 ,  G01S5/06 ,  G01S11/00 ,  G01S13/765 ,  H04L27/2695 ,  H04W4/80

    Abstract: Techniques and systems for position determination using narrowband signals are disclosed. A disclosed technique includes receiving, at a wireless device, signals that are transmitted at different times, each of the signals having a different carrier frequency and representing a different subchannel of a wireless channel; determining estimated magnitudes of the subchannels based respectively on the signals; determining estimated group delays of the subchannels based respectively on the signals; determining an estimated channel frequency response of the wireless channel based on the estimated magnitudes and the estimated group delays; determining a propagation delay of the signals based on the estimated channel frequency response; and generating position information based on the propagation delay.

    Abstract translation: 公开了使用窄带信号进行位置确定的技术和系统。 所公开的技术包括在无线设备处接收在不同时间发送的信号，每个信号具有不同的载波频率并且表示无线信道的不同子信道; 基于信号确定子信道的估计幅度; 分别基于信号确定子信道的估计组延迟; 基于估计的幅度和估计的组延迟来确定无线信道的估计信道频率响应; 基于估计的信道频率响应确定信号的传播延迟; 以及基于传播延迟生成位置信息。

    Programming Schemes for Multi-Level Analog Memory Cells
    68.
    发明申请
    Programming Schemes for Multi-Level Analog Memory Cells 审中-公开
    多级模拟存储单元的编程方案

    公开(公告)号：US20160372184A1

    公开(公告)日：2016-12-22

    申请号：US15256992

    申请日：2016-09-06

    Applicant: Apple Inc.

    Inventor： Ofir Shalvi ,  Naftali Sommer ,  Dotan Sokolov ,  Yoav Kasorla

    IPC: G11C11/56 ,  H03M13/29 ,  G11C29/52 ,  G11C16/34 ,  G06F11/10

    CPC classification number: G11C11/5628 ,  G06F11/1008 ,  G06F11/1068 ,  G11C11/56 ,  G11C16/34 ,  G11C16/3459 ,  G11C29/00 ,  G11C29/52 ,  H03M13/2906

    Abstract: A method for data storage includes storing first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels. Second data bits are stored in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits. A storage strategy is selected responsively to a difference between the first and second times. The storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits.

    Abstract translation: 一种用于数据存储的方法包括：通过对存储器单元进行编程来采用各自的第一编程级别，来将第一数据位在第一时间存储在一组多位模拟存储单元中。 第二数据位通过对存储器单元进行编程以采取依赖于第一编程电平和第二数据位的相应的第二编程电平而在比第一时间晚的第二时间存储在存储单元组中。 响应于第一次和第二次之间的差异选择存储策略。 将存储策略应用于从第一数据位和第二数据位中选择的至少一组数据位。

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