公开(公告)号：US06555880B2

公开(公告)日：2003-04-29

申请号：US09875187

申请日：2001-06-07

申请人： Cyril Cabral, Jr. ,  Kevin Kok Chan ,  Guy Moshe Cohen ,  Kathryn Wilder Guarini ,  Christian Lavoie ,  Ronnen Andrew Roy ,  Paul Michael Solomon

发明人： Cyril Cabral, Jr. ,  Kevin Kok Chan ,  Guy Moshe Cohen ,  Kathryn Wilder Guarini ,  Christian Lavoie ,  Ronnen Andrew Roy ,  Paul Michael Solomon

IPC分类号： H01L31119

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28525 ,  H01L29/41783

摘要： A semiconductor structure includes raised source and drain regions, where the raised source and drain regions are facet free and unconstrained to have a shape conforming to a same crystallographic axes with respect to each other.

摘要翻译： 半导体结构包括凸起的源极和漏极区域，其中升高的源极和漏极区域是小面自由的并且不受限制地具有与彼此相同的结晶轴的形状。

公开(公告)号：US06448131B1

公开(公告)日：2002-09-10

申请号：US09929182

申请日：2001-08-14

申请人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Guy M. Cohen ,  Ramachandra Divakaruni ,  Christian Lavoie ,  Fenton R. McFeely

发明人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Guy M. Cohen ,  Ramachandra Divakaruni ,  Christian Lavoie ,  Fenton R. McFeely

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L28/84 ,  H01L29/66181 ,  Y10S438/964

摘要： A method for increasing the trench capacitor surface area is provided. The method, which utilizes a metal silicide to roughen the trench walls, increases capacitance due to the increase in the trench surface area after the silicide has been removed. The roughening of the trench walls can be controlled by varying one or more of the following parameters: the density of the metal, the metal film thickness, the silicide phase, and the choice of the metal. Once the metal is deposited in the trench, the method is self-limited. Shrinking the trench to its original width can be obtained by subsequent silicon deposition or by diffusion of silicon from a cap layer through the silicide.

摘要翻译： 提供了一种用于增加沟槽电容器表面积的方法。 利用金属硅化物粗糙化沟槽壁的方法由于硅化物被去除之后的沟槽表面积的增加而增加了电容。 可以通过改变一个或多个以下参数来控制沟槽壁的粗糙化：金属的密度，金属膜厚度，硅化物相以及金属的选择。 一旦金属沉积在沟槽中，该方法是自限制的。 通过随后的硅沉积或通过硅化物从盖层扩散硅可以获得将沟槽缩小至原始宽度。

公开(公告)号：US08927422B2

公开(公告)日：2015-01-06

申请号：US13525401

申请日：2012-06-18

申请人： Emre Alptekin ,  Nathaniel Berliner ,  Christian Lavoie ,  Kam-Leung Lee ,  Ahmet Serkan Ozcan

发明人： Emre Alptekin ,  Nathaniel Berliner ,  Christian Lavoie ,  Kam-Leung Lee ,  Ahmet Serkan Ozcan

IPC分类号： H01L21/44 ,  H01L21/31 ,  H01L21/285 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238

CPC分类号： H01L21/28518 ,  H01L21/02063 ,  H01L21/28525 ,  H01L21/76814 ,  H01L21/823814 ,  H01L23/485 ,  H01L29/665 ,  H01L29/66575 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a raised silicide contact including depositing a layer of silicon at a bottom of a contract trench using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide, a width of the silicide and the contact trench are substantially equal; heating the silicide including the silicon layer to a temperature from about 300° C. to about 950° C. in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate.

摘要翻译： 一种用于形成高硅化物接触的方法，包括使用气体簇注入技术在合同沟槽的底部沉积硅层，所述气体簇注入技术加速硅原子簇，导致它们穿过硅化物顶表面上的表面氧化物，宽度 的硅化物和接触沟槽基本相等; 将包含硅层的硅化物在惰性气氛中加热至约300℃至约950℃的温度，使来自硅层的硅与部分形成在含硅衬底中的剩余硅化物反应; 以及从所述硅层形成凸起的硅化物，其中所述凸起的硅化物的厚度大于所述硅化物的厚度，并且所述硅化物在所述含硅衬底的顶表面上方突出。

公开(公告)号：US08895379B2

公开(公告)日：2014-11-25

申请号：US13344806

申请日：2012-01-06

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Christian Lavoie

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Christian Lavoie

IPC分类号： H01L21/336

CPC分类号： H01L29/66515 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L23/485 ,  H01L27/0883 ,  H01L27/1052 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.

摘要翻译： 结构具有至少一个场效应晶体管，其栅极堆叠设置在与栅极堆叠相邻的凸起的源极漏极结构之间。 栅极堆叠和升高的源极漏极结构设置在半导体材料的表面上。 该结构还包括覆盖栅极叠层和升高的源极漏极结构的场介电层，以及延伸穿过场电介质层的第一接触金属和第二接触金属。 第一接触金属终止在通过第一凸起源极漏极结构的顶表面形成的第一沟槽中，并且第二接触金属终止于通过第二凸起源极漏极结构的顶表面形成的第二沟槽中。 每个沟槽具有形成在沟槽的至少一部分的侧壁和底表面上的硅化物。 还公开了制造该结构的方法。

公开(公告)号：US08889537B2

公开(公告)日：2014-11-18

申请号：US12833272

申请日：2010-07-09

申请人： Cryil Cabral, Jr. ,  John M. Cotte ,  Dinesh R. Koli ,  Laura L. Kosbar ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Stephen M. Rossnagel ,  Zhen Zhang

发明人： Cryil Cabral, Jr. ,  John M. Cotte ,  Dinesh R. Koli ,  Laura L. Kosbar ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Stephen M. Rossnagel ,  Zhen Zhang

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L29/45

CPC分类号： H01L21/28512 ,  H01L21/28518 ,  H01L29/456

摘要： A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer.

摘要翻译： 在半导体材料和硅化物层之间的结处形成分离的界面掺杂剂层的方法包括在半导体材料上沉积掺杂的金属层; 退火所述掺杂金属层和所述半导体材料，其中所述退火使所述掺杂金属层的一部分和所述半导体材料的一部分反应以在所述半导体材料上形成所述硅化物层，并且其中所述退火还导致所述分离的界面掺杂剂 层，以形成在半导体材料和硅化物层之间，分离的界面掺杂剂层包含来自掺杂金属层的掺杂剂; 以及从所述硅化物层去除所述掺杂金属层的未反应部分。

公开(公告)号：US08859316B2

公开(公告)日：2014-10-14

申请号：US12825527

申请日：2010-06-29

申请人： Dechao Guo ,  Christian Lavoie ,  Christine Ouyang Qiqing ,  Yanning Sun ,  Zhen Zhang

发明人： Dechao Guo ,  Christian Lavoie ,  Christine Ouyang Qiqing ,  Yanning Sun ,  Zhen Zhang

IPC分类号： H01L21/00 ,  H01L29/06 ,  G01N27/414

CPC分类号： G01N27/4145 ,  G01N27/4146 ,  H01L29/0673

摘要： A Schottky junction silicon nanowire field-effect biosensor/molecule detector with a nanowire thickness of 10 nanometer or less and an aligned source/drain workfunction for increased sensitivity. The nanowire channel is coated with a surface treatment to which a molecule of interest absorbs, which modulates the conductivity of the channel between the Schottky junctions sufficiently to qualitatively and quantitatively measure the presence and amount of the molecule.

摘要翻译： 肖特基结的硅纳米线场效应生物传感器/分子检测器，纳米线厚度为10纳米或更小，并具有对准的源极/漏极功能，以提高灵敏度。 纳米线通道涂覆有目标分子吸收的表面处理，其可以充分调节肖特基结之间的通道的电导率以定性和定量地测量分子的存在和量。

公开(公告)号：US08741753B2

公开(公告)日：2014-06-03

申请号：US13611736

申请日：2012-09-12

申请人： Kisik Choi ,  Christian Lavoie ,  Paul M. Solomon ,  Bin Yang ,  Zhen Zhang

发明人： Kisik Choi ,  Christian Lavoie ,  Paul M. Solomon ,  Bin Yang ,  Zhen Zhang

IPC分类号： H01L21/20 ,  H01L21/3205 ,  H01L21/00

CPC分类号： H01L29/7833 ,  H01L21/28512 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

摘要： A device includes a gate stack formed over a channel in a semiconductor substrate. The gate stack includes a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The device further includes source and drain contacts adjacent to the channel. The source and drain contacts each include a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal.

摘要翻译： 一种器件包括形成在半导体衬底中的沟道上方的栅叠层。 栅极堆叠包括栅极绝缘体材料层，覆盖栅极绝缘体材料层的栅极金属层和覆盖层带边缘栅极金属的接触金属层。 该装置还包括邻近通道的源极和漏极接触。 源极和漏极触点各自包括覆盖并与半导体衬底的掺杂区域直接电接触的栅极金属层以及覆盖在栅极金属层上的接触金属层。

公开(公告)号：US20140073130A1

公开(公告)日：2014-03-13

申请号：US13613579

申请日：2012-09-13

申请人： David F. Hilscher ,  Christian Lavoie ,  Ahmet S. Ozcan

发明人： David F. Hilscher ,  Christian Lavoie ,  Ahmet S. Ozcan

IPC分类号： H01L21/3205

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of performing a silicide contact process comprises a forming a nickel-platinum alloy (NiPt) layer over a semiconductor device structure; performing a first rapid thermal anneal (RTA) so as to react portions of the NiPt layer in contact with semiconductor regions of the semiconductor device structure, thereby forming metal rich silicide regions; performing a first wet etch to remove at least a nickel constituent of unreacted portions of the NiPt layer; performing a second wet etch using a dilute Aqua Regia treatment comprising nitric acid (HNO3), hydrochloric acid (HCl) and water (H2O) to remove any residual platinum material from the unreacted portions of the NiPt layer; and following the dilute Aqua Regia treatment, performing a second RTA to form final silicide contact regions from the metal rich silicide regions.

摘要翻译： 执行硅化物接触工艺的方法包括在半导体器件结构上形成镍 - 铂合金（NiPt）层; 执行第一快速热退火（RTA），以使NiPt层的与半导体器件结构的半导体区域接触的部分反应，由此形成富金属硅化物区域; 执行第一湿蚀刻以去除至少NiPt层的未反应部分的镍组分; 使用包含硝酸（HNO 3），盐酸（HCl）和水（H 2 O）的稀释Aqua Regia处理进行第二次湿蚀刻以从NiPt层的未反应部分去除任何残余的铂材料; 并且在稀释的Aqua Regia处理之后，执行第二个RTA从富金属硅化物区形成最终的硅化物接触区。

公开(公告)号：US08652963B2

公开(公告)日：2014-02-18

申请号：US13237732

申请日：2011-09-20

申请人： Bin Yang ,  Christian Lavoie ,  Emre Alptekin ,  Ahmet S. Ozcan ,  Cung D. Tran ,  Mark Raymond

发明人： Bin Yang ,  Christian Lavoie ,  Emre Alptekin ,  Ahmet S. Ozcan ,  Cung D. Tran ,  Mark Raymond

IPC分类号： H01L21/44

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L29/6659 ,  H01L29/7833

摘要： An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.

摘要翻译： 提供具有均匀厚度的硅化物层的MOSFET器件及其制造方法。 一种这样的方法包括在硅半导体衬底的表面上的宽且窄的接触沟槽上沉积金属层。 在金属/硅界面处形成均匀薄的无定形混合合金层时，除去过量的（未反应的）金属。 该器件被退火以促进在衬底表面上形成薄的硅化物层，其在宽和窄接触沟槽的底部显示均匀的厚度。

公开(公告)号：US08456011B2

公开(公告)日：2013-06-04

申请号：US13006664

申请日：2011-01-14

申请人： Christian Lavoie ,  Ahmet S. Ozcan ,  Zhen Zhang ,  Bin Yang

发明人： Christian Lavoie ,  Ahmet S. Ozcan ,  Zhen Zhang ,  Bin Yang

IPC分类号： H01L23/532

CPC分类号： H01L21/768 ,  H01L21/28518 ,  H01L23/485 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66575 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm.