公开(公告)号：US20120033211A1

公开(公告)日：2012-02-09

申请号：US13204132

申请日：2011-08-05

申请人： William Wang ,  Chung-Cheng Chou ,  Che-Liang Tsai

发明人： William Wang ,  Chung-Cheng Chou ,  Che-Liang Tsai

IPC分类号： G01N21/55 ,  G01J3/28

CPC分类号： G01N21/4795 ,  A61B5/0066 ,  A61B5/0073 ,  G01B9/02019 ,  G01B9/02027 ,  G01B9/02091 ,  G01B2290/45

摘要： A large area optical diagnosis apparatus and the operating method thereof are disclosed. The large area optical diagnosis apparatus includes a light source, a light path structure, and a sensing module. The light source is used to at least emit a coherent light. The light path structure includes a plurality of optical units used for dividing the coherent light into a plurality of first incident lights and a plurality of second incident lights. The plurality of first incident lights are emitted toward an object to be diagnosed and the plurality of second incident lights are emitted toward a reference end. The object to be diagnosed and the reference end reflect the plurality of first incident lights and the plurality of second incident lights to be a plurality of reflected lights. The sensing module senses the plurality of reflected lights to generate a sensing result related to the object to be diagnosed.

摘要翻译： 公开了一种大面积光诊断装置及其操作方法。 大面积光诊断装置包括光源，光路结构和感测模块。 光源用于至少发出相干光。 光路结构包括用于将相干光分为多个第一入射光和多个第二入射光的多个光学单元。 多个第一入射光朝向被诊断对象发射，并且多个第二入射光朝向参考端发射。 要诊断的对象和参考端将多个第一入射光和多个第二入射光反射成多个反射光。 感测模块​​感测多个反射光以产生与被诊断对象相关的感测结果。

公开(公告)号：US20110306835A1

公开(公告)日：2011-12-15

申请号：US13157832

申请日：2011-06-10

申请人： Chung-Cheng Chou ,  William Wang

发明人： Chung-Cheng Chou ,  William Wang

IPC分类号： A61B1/005

CPC分类号： A61B1/008 ,  A61B1/0051 ,  A61B1/0125

摘要： An endoscopy apparatus having high degree of motion freedom and the operating method thereof are disclosed. The endoscopy apparatus having high degree of motion freedom includes a multi-stage endoscopy module and a control module. The multi-stage endoscopy module includes at least a first endoscopy unit and a second endoscopy unit. The first endoscopy unit and the second endoscopy unit can provide a first bending and a second bending respectively. The second bending is larger than the first bending. When the multi-stage endoscopy module moves to a region near a target observing position, the control module will control the second endoscopy unit to generate slight deformation to observe a real-time state of the target observing position.

摘要翻译： 公开了具有高自由度的内窥镜装置及其操作方法。 具有高度运动自由度的内窥镜检查装置包括多级内窥镜检查模块和控制模块。 所述多级内窥镜检查模块至少包括第一内窥镜检查单元和第二内窥镜检查单元。 第一内镜检查单元和第二内窥镜检查单元可以分别提供第一弯曲和第二弯曲。 第二次弯曲大于第一次弯曲。 当多级内窥镜模块移动到目标观察位置附近的区域时，控制模块将控制第二内窥镜单元产生轻微的变形以观察目标观察位置的实时状态。

公开(公告)号：US07829388B2

公开(公告)日：2010-11-09

申请号：US12694239

申请日：2010-01-26

申请人： Chin-Yung Chen ,  Chia-Hung Hsu ,  William Wang ,  Chung-Cheng Chou

发明人： Chin-Yung Chen ,  Chia-Hung Hsu ,  William Wang ,  Chung-Cheng Chou

IPC分类号： H01L21/00

CPC分类号： H01L23/3735 ,  H01L23/3677 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The invention discloses an integrated circuit package. The integrated circuit package comprises a substrate having a first surface and a second surface opposite thereto and a first hole passing through the substrate from the first surface to the second surface. A plurality of conductive lines is disposed on a portion of the second surface of the substrate. A semiconductor chip is disposed above the second surface of the substrate, wherein a chamber is formed between the semiconductor chip and the substrate. A plurality of bonding pads are disposed on a side of the semiconductor chip which is toward the second surface of the substrate, wherein at least one of the bonding pads are electrically connected to one of the plurality of conductive lines. A first heat dissipation layer is disposed in the first hole, and extends into the chamber. A method for fabricating the integrated circuit package is also provided.

摘要翻译： 本发明公开了一种集成电路封装。 集成电路封装包括具有第一表面和与其相对的第二表面的基板以及从第一表面到第二表面穿过基板的第一孔。 多个导电线设置在基板的第二表面的一部分上。 半导体芯片设置在衬底的第二表面上方，其中在半导体芯片和衬底之间形成腔室。 多个接合焊盘设置在半导体芯片的朝向衬底的第二表面的一侧上，其中至少一个接合焊盘电连接到多条导线之一。 第一散热层设置在第一孔中并延伸到腔室中。 还提供了一种用于制造集成电路封装的方法。

公开(公告)号：US20100259507A1

公开(公告)日：2010-10-14

申请号：US12718643

申请日：2010-03-05

申请人： Meng-Shin Yen ,  William Wang ,  Chung-Cheng Chou

发明人： Meng-Shin Yen ,  William Wang ,  Chung-Cheng Chou

IPC分类号： G06F3/042

CPC分类号： G06F3/0421

摘要： An optical touch apparatus and operating method thereof are disclosed. The optical touch apparatus comprises an optical module, a light sensing module, and a processing module. The optical module and the light sensing module are set at a first side and an opposite second side of a surface of the optical touch apparatus respectively. The optical module receives a light source and uniformly emits a plurality of lights. When at least one of the plurality of lights is blocked by an object above the surface, the light sensing module generates a sensing result based on the condition of receiving the plurality of lights. The processing module determines a touch point location corresponding to the object on the surface based on the sensing result.

摘要翻译： 公开了一种光学触摸装置及其操作方法。 光学触摸装置包括光学模块，光感测模块和处理模块。 光学模块和感光模块分别设置在光学触摸装置的表面的第一侧和相对的第二侧。 光学模块接收光源并均匀地发射多个光。 当多个光中的至少一个光被表面上方的物体阻挡时，光感测模块基于接收多个光的条件产生感测结果。 处理模块基于感测结果确定与表面上的对象相对应的触摸点位置。

公开(公告)号：US07804169B2

公开(公告)日：2010-09-28

申请号：US12102439

申请日：2008-04-14

申请人： Chin-Yung Chen ,  Chia-Hung Hsu ,  William Wang ,  Chung-Cheng Chou

发明人： Chin-Yung Chen ,  Chia-Hung Hsu ,  William Wang ,  Chung-Cheng Chou

IPC分类号： H01L23/10

CPC分类号： H01L23/3735 ,  H01L23/3677 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The invention discloses an integrated circuit package. The integrated circuit package comprises a substrate having a first surface and a second surface opposite thereto and a first hole passing through the substrate from the first surface to the second surface. A plurality of conductive lines is disposed on a portion of the second surface of the substrate. A semiconductor chip is disposed above the second surface of the substrate, wherein a chamber is formed between the semiconductor chip and the substrate. A plurality of bonding pads are disposed on a side of the semiconductor chip which is toward the second surface of the substrate, wherein at least one of the bonding pads are electrically connected to one of the plurality of conductive lines. A first heat dissipation layer is disposed in the first hole, and extends into the chamber. A method for fabricating the integrated circuit package is also provided.

公开(公告)号：US20090179326A1

公开(公告)日：2009-07-16

申请号：US12106148

申请日：2008-04-18

申请人： Ko-Yang Tso ,  Chung-Cheng Chou ,  William Wang ,  Chia-Hung Hsu

发明人： Ko-Yang Tso ,  Chung-Cheng Chou ,  William Wang ,  Chia-Hung Hsu

IPC分类号： H01L23/49

CPC分类号： H01L24/06 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The invention provides a semiconductor device package. The package includes a chip disposed on a supported board and a conductive path formed between the chip and the supported board, on the backside of the supported board, or on the chip, so that the conductive path does not have to go around a region where the chip is located. Accordingly, the dimensions of the semiconductor device package are reduced.

摘要翻译： 本发明提供一种半导体器件封装。 该封装包括设置在支撑板上的芯片和形成在芯片和支撑板之间，支撑板的背面或芯片上的导电路径，使得导电路径不必绕过 芯片位于。 因此，半导体器件封装的尺寸减小。

公开(公告)号：US20080302664A1

公开(公告)日：2008-12-11

申请号：US12155274

申请日：2008-06-02

申请人： Cheng-Hsien Liu ,  Long Hsu ,  Kuang-Han Chu ,  William Wang ,  Chung-Cheng Chou

发明人： Cheng-Hsien Liu ,  Long Hsu ,  Kuang-Han Chu ,  William Wang ,  Chung-Cheng Chou

IPC分类号： C02F1/469

CPC分类号： G01N27/44713 ,  C02F1/469 ,  C02F2001/46152 ,  C02F2201/4613 ,  G01N2030/285

摘要： An apparatus for driving a fluid includes a substrate, at least one electrode group and a controlling unit. The substrate has at least one plane. The electrode group is disposed on the substrate and includes a first electrode, a second electrode and a third electrode. A projecting position of the second electrode on the plane is disposed between that of the first electrode and that of the third electrode. The controlling unit electrically connected to electrode group is for driving the first to third electrodes. When the controlling unit drives the first to third electrodes to make the first and third electrodes have opposite polarities and to make the second and third electrodes have the same polarity, an electric field produced by the electrode group enables the fluid on the substrate to flow from the first electrode to the third electrode.

摘要翻译： 用于驱动流体的装置包括基板，至少一个电极组和控制单元。 衬底具有至少一个平面。 电极组设置在基板上，并且包括第一电极，第二电极和第三电极。 平面上的第二电极的突出位置设置在第一电极和第三电极的突出位置之间。 电连接到电极组的控制单元用于驱动第一至第三电极。 当控制单元驱动第一至第三电极以使第一和第三电极具有相反的极性并且使得第二和第三电极具有相同的极性时，由电极组产生的电场使得基板上的流体能够从 第一电极到第三电极。

公开(公告)号：US08724420B2

公开(公告)日：2014-05-13

申请号：US13105382

申请日：2011-05-11

申请人： Chiting Cheng ,  Chung-Cheng Chou ,  Tsung-yung Jonathan Chang

发明人： Chiting Cheng ,  Chung-Cheng Chou ,  Tsung-yung Jonathan Chang

IPC分类号： G11C11/413

CPC分类号： G11C11/419 ,  G11C11/41 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028

摘要： An SRAM write assist apparatus comprises a timer unit and a voltage divider. The voltage divider unit is configured to divide a voltage potential down to a lower level. The output of the voltage divider is connected to a memory cell in a write operation. The timer unit is configured to generate a pulse having a width inversely proportional to the voltage potential applied to a memory chip. Furthermore, the timer unit controls the period in which a lower voltage from the output of the voltage divider is applied to the memory cell. Moreover, external level and timing programmable signals can be used to further adjust the voltage divider's ratio and the pulse width from the timer unit. By employing the SRAM write assist apparatus, a memory chip can perform a reliable and fast write operation.

摘要翻译： SRAM写入辅助装置包括定时器单元和分压器。 分压器单元被配置为将电压电位分压到较低电平。 在写入操作中，分压器的输出连接到存储单元。 定时器单元被配置为产生具有与施加到存储芯片的电压电位成反比的宽度的脉冲。 此外，定时器单元控制将来自分压器的输出的较低电压施加到存储单元的周期。 此外，可以使用外部电平和定时可编程信号来进一步调整分压器的比例和来自定时器单元的脉冲宽度。 通过采用SRAM写入辅助装置，存储器芯片可以执行可靠且快速的写入操作。

公开(公告)号：US08575965B2

公开(公告)日：2013-11-05

申请号：US13118060

申请日：2011-05-27

申请人： Chi-Lin Liu ,  Chung-Cheng Chou ,  Yangsyu Lin ,  Hsiao Wen Lu

发明人： Chi-Lin Liu ,  Chung-Cheng Chou ,  Yangsyu Lin ,  Hsiao Wen Lu

IPC分类号： H03K19/096

CPC分类号： G06F1/3287 ,  G06F1/3237 ,  Y02D10/128 ,  Y02D10/171

摘要： An internal clock gating apparatus comprises a static logic block and a domino logic block. The static logic block is configured to receive a clock signal and a clock enable signal. The domino logic block is configured to receive the clock signal and a control signal from an output of the static logic block. The static logic block and the domino logic block are further configured such that an output of the domino logic block generates a signal similar to the clock signal in phase when the clock enable signal has a logic high state. On the other hand, the output of the domino logic block generates a logic low signal when the clock enable signal has a logic low state. Furthermore, the static logic block and the domino logic block can reduce the setup time and delay time of the internal clock gating apparatus respectively.

摘要翻译： 内部时钟选通装置包括静态逻辑块和多米诺逻辑块。 静态逻辑块被配置为接收时钟信号和时钟使能信号。 多米诺骨牌逻辑块被配置为从静态逻辑块的输出接收时钟信号和控制信号。 静态逻辑块和多米诺逻辑块进一步被配置为使得当时钟使能信号具有逻辑高状态时，多米诺骨牌逻辑块的输出产生类似时钟信号的相位信号。 另一方面，当时钟使能信号具有逻辑低电平状态时，多米诺逻辑块的输出产生逻辑低电平信号。 此外，静态逻辑块和多米诺逻辑块可以分别减少内部时钟门控装置的建立时间和延迟时间。

公开(公告)号：US20120299622A1

公开(公告)日：2012-11-29

申请号：US13118060

申请日：2011-05-27

申请人： Chi-Lin Liu ,  Chung-Cheng Chou ,  Yangsyu Lin ,  Hsiao Wen Lu

发明人： Chi-Lin Liu ,  Chung-Cheng Chou ,  Yangsyu Lin ,  Hsiao Wen Lu

IPC分类号： H03K19/096

CPC分类号： G06F1/3287 ,  G06F1/3237 ,  Y02D10/128 ,  Y02D10/171

摘要： An internal clock gating apparatus comprises a static logic block and a domino logic block. The static logic block is configured to receive a clock signal and a clock enable signal. The domino logic block is configured to receive the clock signal and a control signal from an output of the static logic block. The static logic block and the domino logic block are further configured such that an output of the domino logic block generates a signal similar to the clock signal in phase when the clock enable signal has a logic high state. On the other hand, the output of the domino logic block generates a logic low signal when the clock enable signal has a logic low state. Furthermore, the static logic block and the domino logic block can reduce the setup time and delay time of the internal clock gating apparatus respectively.

摘要翻译： 内部时钟选通装置包括静态逻辑块和多米诺逻辑块。 静态逻辑块被配置为接收时钟信号和时钟使能信号。 多米诺骨牌逻辑块被配置为从静态逻辑块的输出接收时钟信号和控制信号。 静态逻辑块和多米诺逻辑块进一步被配置为使得当时钟使能信号具有逻辑高状态时，多米诺骨牌逻辑块的输出产生类似时钟信号的相位信号。 另一方面，当时钟使能信号具有逻辑低电平状态时，多米诺逻辑块的输出产生逻辑低电平信号。 此外，静态逻辑块和多米诺逻辑块可以分别减少内部时钟门控装置的建立时间和延迟时间。