公开(公告)号：US20090176334A1

公开(公告)日：2009-07-09

申请号：US12007008

申请日：2008-01-04

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L21/00

CPC分类号： H01L21/4867 ,  H01L21/481 ,  H01L21/561 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49833 ,  H01L24/27 ,  H01L24/48 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/8385 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Disclosed is a method for forming a die-attach layer during semiconductor packaging processes. A chip carrier includes a substrate core and a stiffener. Top surface of the substrate core includes a plurality of die-attaching units and a peripheral area enclosed by the stiffener. A non-planar printing stencil is also provided. When the non-planar printing stencil is pressed against the chip carrier, the non-planar printing stencil is compliantly in contact with the substrate core and the stiffener and a plurality of printing openings of the non-planar printing stencil exposes the substrate core within the die-attaching units. During stencil printing, die-attach material fills in the printing openings to directly adhere to the substrate core. Therefore, the warpage of the substrate core is restrained to avoid bleeding of die-attach material so that die-attach materials can be formed as a die-attach layer with a uniform thickness on core-exposed chip carrier with lower costs. Additionally, the chip carrier will not be deformed during semiconductor packaging processes.

摘要翻译： 公开了一种在半导体封装工艺期间形成管芯附着层的方法。 芯片载体包括衬底芯和加强件。 基板芯的顶表面包括多个模具附接单元和由加强件包围的周边区域。 还提供了非平面印刷模版。 当非平面印刷模版被压靠在芯片载体上时，非平面印刷模板顺从地与衬底芯和加强件接触，并且非平面印刷模板的多个印刷开口将衬底芯暴露在 模具连接单元。 在模版印刷期间，芯片附着材料填充在印刷开口中以直接粘附到基板芯上。 因此，抑制基板芯的翘曲，以避免芯片附着材料的渗出，使得芯片附着材料可以以较低的成本形成为具有均匀厚度的裸芯片载体上的芯片附着层。 此外，芯片载体在半导体封装工艺期间不会变形。

公开(公告)号：US07547974B2

公开(公告)日：2009-06-16

申请号：US11640262

申请日：2006-12-18

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/48 ,  H05K1/00 ,  H05K7/00

CPC分类号： H05K1/0271 ,  H01L23/498 ,  H01L2924/0002 ,  H05K1/0265 ,  H05K3/28 ,  H05K2201/09672 ,  H05K2201/098 ,  H05K2203/0733 ,  H01L2924/00

摘要： A wiring substrate with tensile-strength enhanced traces primarily comprises a core layer, a plurality of connecting pads, a plurality of traces, and a solder resist where the connecting pads and the traces are disposed on a top of the core layer. The solder resist is formed over the top of the core layer to cover the traces with the connecting pads partially or completely exposed. Furthermore, the traces have I-shaped cross sections to enhance the tensile strength of the traces.

摘要翻译： 具有拉伸强度增强迹线的布线基板主要包括芯层，多个连接焊盘，多个迹线和阻焊层，其中连接焊盘和迹线设置在芯层的顶部。 阻焊层形成在芯层的顶部上，以覆盖具有部分或完全暴露的连接焊盘的迹线。 此外，迹线具有I形横截面以增强迹线的拉伸强度。

公开(公告)号：US20090127687A1

公开(公告)日：2009-05-21

申请号：US11984782

申请日：2007-11-21

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/48

CPC分类号： H01L23/13 ,  H01L23/4951 ,  H01L23/49555 ,  H01L23/49816 ,  H01L23/562 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device having package-on-package (POP) configuration, primarily comprises a plurality of vertically stacked semiconductor packages and a plurality of electrical connecting components such as solder paste to electrically connect the external terminals of the semiconductor packages such as external leads of leadframes. Each semiconductor package has an encapsulant to encapsulate at least a chip where the encapsulant is movable with respect to the electrical connecting components to absorb the stresses between the vertically stacked semiconductor packages. In one embodiment, a stress-releasing layer is interposed between the vertically stacked semiconductor packages.

摘要翻译： 具有封装封装（POP）配置的半导体器件主要包括多个垂直堆叠的半导体封装和多个电连接部件，例如焊膏，以电连接半导体封装的外部端子，例如引线框的外部引线 。 每个半导体封装具有密封剂以封装至少一个芯片，其中密封剂相对于电连接部件可移动，以吸收垂直堆叠的半导体封装之间的应力。 在一个实施例中，应力释放层介于垂直堆叠的半导体封装之间。

公开(公告)号：US07479704B2

公开(公告)日：2009-01-20

申请号：US11651610

申请日：2007-01-10

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/48

CPC分类号： H05K1/111 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K2201/10734 ,  H05K2201/2072 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A substrate improving immobilization of ball pads for BGA packages mainly comprises a substrate core, a plurality of ball pads and a solder resist layer. Each of the ball pads has a metal pad and at least a metal nail. The metal pads are adhered on a surface of the substrate core and the metal nails are embedded into but not penetrate the substrate core. The solder resist layer is formed over the substrate core and exposes the metal pads. By utilizing the shapes of the ball pads to increase bonding area between the ball pads and the substrate core, a separation or crack occurring at the interface between the metal pads and the substrate core can be substantially avoided.

摘要翻译： 提高BGA封装的球垫的固定的基板主要包括基底芯，多个球垫和阻焊层。 每个球垫具有金属垫和至少一金属钉。 金属焊盘粘附在基板芯的表面上，并且金属钉被嵌入而不穿透基板芯。 阻焊层形成在衬底芯上并暴露金属焊盘。 通过利用球垫的形状来增加球垫和衬底芯之间的结合面积，可以基本上避免在金属垫和衬底芯之间的界面处发生的分离或裂纹。

公开(公告)号：US20080296751A1

公开(公告)日：2008-12-04

申请号：US11806031

申请日：2007-05-29

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/48

CPC分类号： H01L23/13 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/564 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/4912 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15159 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package is revealed, primarily comprising a substrate, a chip disposed on the substrate, and an encapsulant to encapsulate the chip. The substrate has a plurality of dimples formed in its top surface thereof without penetrating through the substrate and located at a non-wiring region outside a chip mounting region. Therefore, without changing the appearance of the semiconductor package, the diffusion path of moisture and the adhesive strength between the encapsulant and the substrate can be increased to achieve functions of anti-humidity and anti-delamination.

摘要翻译： 揭示了半导体封装，主要包括衬底，设置在衬底上的芯片以及封装芯片的密封剂。 基板在其顶表面上形成多个凹坑，而不穿透基板并位于芯片安装区域外的非布线区域。 因此，在不改变半导体封装的外观的情况下，可以增加水分的扩散路径和密封剂与基板之间的粘合强度，以实现防湿和防脱层的功能。

公开(公告)号：US20080237855A1

公开(公告)日：2008-10-02

申请号：US11727902

申请日：2007-03-28

申请人： Wen-Jeng Fan ,  Tsai-Chuan Yu

发明人： Wen-Jeng Fan ,  Tsai-Chuan Yu

IPC分类号： H01L23/488

CPC分类号： H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K3/3436 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A BGA package and a substrate for the package are disclosed. A chip is disposed on a top surface of the substrate. A plurality of solder balls are disposed on a plurality of ball pads formed on a bottom surface of the substrate. The substrate has at least a core layer with a plurality of corner cavities filled with low-modulus materials as stress buffer. Additionally, some of the ball pads at the corners of the substrate are disposed under the corner cavities.

摘要翻译： 公开了一种用于封装的BGA封装和衬底。 芯片设置在基板的顶表面上。 多个焊球设置在形成在基板的底表面上的多个球垫上。 衬底至少具有芯层，其具有填充有低模量材料作为应力缓冲器的多个角腔。 此外，基板的角部处的一些球垫设置在角空腔的下方。

公开(公告)号：US20080119012A1

公开(公告)日：2008-05-22

申请号：US11600925

申请日：2006-11-17

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L21/00

CPC分类号： H01L21/67126 ,  H01L21/561 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A MAP (Mold Array Process) for chip encapsulation is disclosed in this invention. First, a substrate strip having a plurality of units is provided. A plurality of chips are disposed on the substrate strip and then an encapsulant is formed made by transfer molding to continuously encapsulate the chips on a plurality of units. Therein, the substrate strip includes at least a first row of units in a one-dimensional array and at least a second row of units in a one-dimensional array and connected with the first row of units in parallel, and the cutting lines between the first row of units are not aligned with those between the second row of units so that the first and second rows of units are disposed in a non-two-dimensional array. Therefore, the mold flows on the cutting lines and on centers of the chips can be balanced merely by means of modifying arrangement of the units without adding obstructions or other extra components to solve conventional encapsulation bubbles generated at sides of the chips.

摘要翻译： 在本发明中公开了用于芯片封装的MAP（模具阵列工艺）。 首先，提供具有多个单元的基板条。 多个芯片设置在基板条上，然后通过传递模塑形成密封剂以将芯片连续地封装在多个单元上。 其中，衬底条包括一维阵列中的至少第一排单元和一维阵列中的至少第二排单元，并且与第一排单元并联连接，并且切割线 第一排单元不与第二排单元之间的单元对齐，使得第一和第二排单元以非二维阵列布置。 因此，模具在切割线上流动并且芯片的中心可以仅通过改变单元的布置来平衡，而不增加障碍物或其他额外的部件来解决在芯片的侧面产生的常规封装气泡。

公开(公告)号：US20080057622A1

公开(公告)日：2008-03-06

申请号：US11514350

申请日：2006-09-01

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L21/00

CPC分类号： H01L21/565 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A MAP (Mold-Array-Process) type semiconductor package mainly includes a chip carrier, at least a chip, and an encapsulant. The chip is disposed on the carrier and is electrically connected to the chip carrier. The encapsulant completely covers the upper surface of the chip carrier and encapsulates the chip. Therein, the encapsulant has two mold-flow constraining portions adjacent two opposite sides of the encapsulant, which are lower than the central top surface of the encapsulant and vertically aligned to the corresponding sawed sides of the chip carrier. Therefore, by changing the shape of the encapsulant, the mold flows on the chip and at the sides of the chip carrier will be the balanced to solve encapsulated bubble(s) formed on the rear side of the chip during MAP packaging, and disposition of conventional barrier components will be eliminated.

摘要翻译： MAP（模具 - 阵列 - 工艺）型半导体封装主要包括芯片载体，至少芯片和密封剂。 芯片设置在载体上并与芯片载体电连接。 密封剂完全覆盖芯片载体的上表面并封装芯片。 其中，密封剂具有与密封剂的两个相对侧相邻的两个模流限制部分，其低于密封剂的中心顶表面并且垂直对齐于芯片载体的相应的锯边。 因此，通过改变密封剂的形状，模具在芯片上流动，并且在芯片载体的侧面将平衡以解决在MAP封装期间在芯片的后侧形成的封装的气泡，并且处理 常规屏障组件将被消除。

公开(公告)号：US20070278671A1

公开(公告)日：2007-12-06

申请号：US11445158

申请日：2006-06-02

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3128 ,  H01L23/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2924/00

摘要： An IC package structure of die face up or die face down is provided with adding the occupied area of die-attaching material. The die-attaching layer is distributed the surface of the substrate exposed by a die and configured for absorbing the thermal stress induced from thermal expansion mismatch of materials generated during a board level temperature cycle test.

摘要翻译： 提供了模具正面朝下或面朝下的IC封装结构，增加了模具附着材料的占用面积。 管芯安装层分布在由管芯暴露的衬底的表面上，并且被配置为吸收由板级温度循环测试期间产生的材料的热膨胀失配引起的热应力。