公开(公告)号：US07768815B2

公开(公告)日：2010-08-03

申请号：US11161941

申请日：2005-08-23

申请人： Fen Chen ,  Richard S. Kontra ,  Tom C. Lee ,  Theodore M. Levin ,  Christopher D. Muzzy ,  Timothy D. Sullivan

发明人： Fen Chen ,  Richard S. Kontra ,  Tom C. Lee ,  Theodore M. Levin ,  Christopher D. Muzzy ,  Timothy D. Sullivan

IPC分类号： G11C13/00

CPC分类号： G11C13/0009 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/04 ,  G11C13/047 ,  G11C2013/0054 ,  H01L45/1213 ,  H01L45/145

摘要： A structure and a method for operating the same. The method comprises providing a resistive/reflective region on a substrate, wherein the resistive/reflective region comprises a material having a characteristic of changing the material's reflectance due to the material absorbing heat; sending an electric current through the resistive/reflective region so as to cause a reflectance change in the resistive/reflective region from a first reflectance value to a second reflectance value different from the first reflectance value; and optically reading the reflectance change in the resistive/reflective region.

摘要翻译： 一种结构及其操作方法。 该方法包括在衬底上提供电阻/反射区域，其中电阻/反射区域包括具有由于材料吸收热而改变材料的反射率的特性的材料; 发送电流通过电阻/反射区域，以使电阻/反射区域的反射率变化从第一反射率值到不同于第一反射率值的第二反射率值; 并且光学地读取电阻/反射区域中的反射率变化。

公开(公告)号：US20100019330A1

公开(公告)日：2010-01-28

申请号：US12178766

申请日：2008-07-24

申请人： Ethan H. Cannon ,  Fen Chen

发明人： Ethan H. Cannon ,  Fen Chen

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/0653 ,  H01L21/26506 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7842 ,  H01L29/7848

摘要： Device structures with a self-aligned damage layer and methods of forming such device structures. The device structure first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate. A third doped region of opposite conductivity type laterally separates the first doped region from the second doped region. A gate structure is disposed on a top surface of the substrate and has a vertically stacked relationship with the third doped region. A first crystalline damage layer is defined within the semiconductor material of the substrate. The first crystalline damage layer has a first plurality of voids surrounded by the semiconductor material of the substrate. The first doped region is disposed vertically between the first crystalline damage layer and the top surface of the substrate. The first crystalline damage layer does not extend laterally into the third doped region.

摘要翻译： 具有自对准损伤层的装置结构和形成这种装置结构的方法。 该器件结构是限定在衬底的半导体材料中的第一导电类型的第一和第二掺杂区域。 相反导电类型的第三掺杂区域将第一掺杂区域与第二掺杂区域横向分离。 栅极结构设置在衬底的顶表面上，并且与第三掺杂区域具有垂直堆叠的关系。 第一晶体损伤层被限定在衬底的半导体材料内。 第一晶体损伤层具有由衬底的半导体材料包围的第一多个空隙。 第一掺杂区域垂直地设置在第一晶体损伤层和衬底的顶表面之间。 第一晶体损伤层不横向延伸到第三掺杂区域。

公开(公告)号：US20090212431A1

公开(公告)日：2009-08-27

申请号：US12035448

申请日：2008-02-22

申请人： Fen Chen ,  Cathryn Jeanne Christiansen ,  Michael Anthony Shinosky ,  Timothy Dooling Sullivan

发明人： Fen Chen ,  Cathryn Jeanne Christiansen ,  Michael Anthony Shinosky ,  Timothy Dooling Sullivan

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76895 ,  H01L23/34 ,  H01L23/522 ,  H01L23/576 ,  H01L2924/0002 ,  Y10S438/917 ,  H01L2924/00

摘要： An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by a region of the dielectric layer; and forming metallic nanoparticles in or on the top surface of the dielectric layer between the first and second wires, the metallic nanoparticles capable of electrically connecting the first wire and the second wire only while the nanoparticles are heated to a temperature greater than room temperature and a voltage is applied between the first and second wires.

摘要翻译： 互连和互连方法。 该方法包括在基底上形成电介质层，介电层具有顶表面和底表面; 在所述电介质层中形成第一线和第二线，所述第一线与所述第二线分离，通过所述介电层的区域; 并且在第一和第二布线之间的电介质层的顶表面中或上方形成金属纳米颗粒，仅在将纳米颗粒加热到大于室温的温度时能够电连接第一布线和第二布线的金属纳米颗粒， 在第一和第二导线之间施加电压。

公开(公告)号：US07571637B2

公开(公告)日：2009-08-11

申请号：US11926241

申请日：2007-10-29

申请人： Fen Chen ,  Kai D. Feng

发明人： Fen Chen ,  Kai D. Feng

IPC分类号： G01N5/02

CPC分类号： G01N27/223

摘要： A design structure for an on-chip real-time moisture detection circuitry for monitoring ingress of moisture into an integrated circuit chip during the operational lifetime of the chip. The moisture detection circuitry includes one or more moisture-sensing units and a common moisture monitor for monitoring the state of each moisture-sensing units. The moisture monitor can be configured to provided a real-time moisture-detected signal for signaling that moisture ingress into the integrated circuit chip has occurred.

摘要翻译： 一种片上实时水分检测电路的设计结构，用于在芯片的使用寿命期间监测水分进入集成电路芯片的情况。 湿度检测电路包括一个或多个湿度感测单元和用于监测每个湿度感测单元的状态的公共湿度监视器。 水分监测器可以被配置为提供实时湿度检测信号，用于发信号通知已经发生湿气进入集成电路芯片。

公开(公告)号：US20080197337A1

公开(公告)日：2008-08-21

申请号：US12109085

申请日：2008-04-24

申请人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

发明人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

IPC分类号： H01L47/00

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C11/5692 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/18 ,  H01L27/101 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145

摘要： The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN thin film resistor embedded within a material having a thermal conductivity of about 1 W/m-K or less; and a non-linear Si-containing device coupled to the resistor. Read and write circuits and operations are also provided in the present application.

摘要翻译： 本发明涉及诸如ROM或EPROM的非易失性存储器，其中存储器的信息密度相对于包括两个逻辑状态器件的常规非易失性存储器而增加。 具体地，本发明的非易失性存储器包括嵌入在热导率为约1W / m-K以下的材料中的SiN / TaN / SiN薄膜电阻器; 以及耦合到电阻器的非线性含Si器件。 读写电路和操作也在本申请中提供。

公开(公告)号：US07381981B2

公开(公告)日：2008-06-03

申请号：US11161332

申请日：2005-07-29

申请人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

发明人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

IPC分类号： H01L29/02 ,  H01L47/00

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C11/5692 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/18 ,  H01L27/101 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145

摘要： The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN thin film resistor embedded within a material having a thermal conductivity of about 1 W/m-K or less; and a non-linear Si-containing device coupled to the resistor. Read and write circuits and operations are also provided in the present application.

摘要翻译： 本发明涉及诸如ROM或EPROM的非易失性存储器，其中存储器的信息密度相对于包括两个逻辑状态器件的常规非易失性存储器而增加。 具体地，本发明的非易失性存储器包括嵌入在热导率为约1W / m-K以下的材料中的SiN / TaN / SiN薄膜电阻器; 以及耦合到电阻器的非线性含Si器件。 读写电路和操作也在本申请中提供。

公开(公告)号：US07378866B2

公开(公告)日：2008-05-27

申请号：US11942396

申请日：2007-11-19

申请人： Fen Chen ,  Kai D Feng ,  Robert J Gautheir ,  Tom C Lee

发明人： Fen Chen ,  Kai D Feng ,  Robert J Gautheir ,  Tom C Lee

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/018571

摘要： A method for trimming impedance matching devices in high-speed circuits includes determining an electrical parameter associated with a first tantalum nitride (TaN) resistor used as an impedance matching device in the circuit under test, and comparing the determined electrical parameter associated with the first TaN resistor to a desired design value of the electrical parameter. The resistance value of the first TaN resistor is altered by application of a trimming voltage thereto, wherein the trimming voltage is based on a voltage-resistance characteristic curve of the first TaN resistor. It is then determined whether the altered resistance value of the first TaN resistor causes the electrical parameter to equal the desired design value thereof, and the altering of the resistance value of the first TaN resistor by application of a trimming voltage is repeated until the electrical parameter equals the desired design value thereof.

公开(公告)号：US20080061902A1

公开(公告)日：2008-03-13

申请号：US11942396

申请日：2007-11-19

申请人： Fen Chen ,  Kai Feng ,  Robert Gautheir ,  Tom Lee

发明人： Fen Chen ,  Kai Feng ,  Robert Gautheir ,  Tom Lee

IPC分类号： H03H7/38

CPC分类号： H03K19/018571

摘要： A method for trimming impedance matching devices in high-speed circuits includes determining an electrical parameter associated with a first tantalum nitride (TaN) resistor used as an impedance matching device in the circuit under test, and comparing the determined electrical parameter associated with the first TaN resistor to a desired design value of the electrical parameter. The resistance value of the first TaN resistor is altered by application of a trimming voltage thereto, wherein the trimming voltage is based on a voltage-resistance characteristic curve of the first TaN resistor. It is then determined whether the altered resistance value of the first TaN resistor causes the electrical parameter to equal the desired design value thereof, and the altering of the resistance value of the first TaN resistor by application of a trimming voltage is repeated until the electrical parameter equals the desired design value thereof.

公开(公告)号：US20070189015A1

公开(公告)日：2007-08-16

申请号：US11508369

申请日：2006-08-23

申请人： Shao-Han Chang ,  Fen Chen

发明人： Shao-Han Chang ,  Fen Chen

IPC分类号： F21V7/00

CPC分类号： F21V29/74 ,  F21V29/004 ,  F21V29/76 ,  F21Y2115/10 ,  G02F1/133603 ,  G02F1/133611

摘要： A light source module includes at least a light source and a housing. The housing includes a base having a slanted reflective surface, a plurality of sidewalls extending out of a peripheral of the base cooperatively defining an opening with the base, the sidewall aligned with a trough of the slanted reflective surface having an inner surface and an outer surface opposite to the inner surface, and a plurality of fin structures formed on the outer surface of the sidewall. The light source is fixed on the inner surface of the sidewall. Light rays emitted from the light source being reflected at the slanted reflective surface toward the opening. A backlight system using the light source module is also provided. The present backlight system has a good heat dissipation capability due to an employment of the present light source module, and can be configured to be a thin body.

摘要翻译： 光源模块至少包括光源和壳体。 壳体包括具有倾斜反射表面的底座，从基座的周边延伸出的多个侧壁协同地限定具有基部的开口，与倾斜反射表面的槽对准的侧壁具有内表面和外表面 与内表面相对，以及形成在侧壁的外表面上的多个翅片结构。 光源固定在侧壁的内表面上。 从光源发射的光线在倾斜的反射面朝向开口反射。 还提供了使用光源模块的背光系统。 由于使用本发明的光源模块，本背光系统具有良好的散热能力，并且可以被配置为薄体。

公开(公告)号：US06800938B2

公开(公告)日：2004-10-05

申请号：US10215121

申请日：2002-08-08

申请人： Fen Chen

发明人： Fen Chen

IPC分类号： H01L2348

CPC分类号： H01L21/76846 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A semiconductor device which includes, between a copper conductive layer and a low-k organic insulator, a barrier layer comprising an amorphous metallic glass, preferably amorphous tantalum-aluminum. A method of making the semiconductor device is also disclosed.

摘要翻译： 一种半导体器件，包括在铜导电层和低k有机绝缘体之间的包含非晶金属玻璃，优选无定形钽 - 铝的阻挡层。 还公开了制造半导体器件的方法。