公开(公告)号：US20070066022A1

公开(公告)日：2007-03-22

申请号：US11233831

申请日：2005-09-22

申请人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Hsiu-Lien Liao

发明人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Hsiu-Lien Liao

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

摘要： A method of fabricating a silicon nitride layer is described. First, a substrate is provided. Then, a silicon nitride layer is formed on the substrate. The silicon nitride layer is UV-cured in an atmosphere lower than the standard atmospheric pressure. Through the UV curing treatment, the tensile stress of the silicon nitride layer is increased.

摘要翻译： 描述了制造氮化硅层的方法。 首先，提供基板。 然后，在基板上形成氮化硅层。 氮化硅层在低于标准大气压的气氛中UV固化。 通过UV固化处理，氮化硅层的拉伸应力增加。

公开(公告)号：US20060199305A1

公开(公告)日：2006-09-07

申请号：US11164488

申请日：2005-11-24

申请人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Tsai-Fu Chen ,  Wen-Han Hung

发明人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Tsai-Fu Chen ,  Wen-Han Hung

IPC分类号： H01L21/00 ,  H01L21/31

CPC分类号： H01L21/0217 ,  C23C16/345 ,  C23C16/56 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/3185 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A method for fabricating an ultra-high tensile-stressed nitride film is disclosed. A PECVD process is first performed to deposit a transitional silicon nitride film over a substrate. The transitional silicon nitride film has a first concentration of hydrogen atoms. The transitional silicon nitride film is subjected to UV curing process for reducing the first concentration of hydrogen atoms to a second concentration of hydrogen atoms.

摘要翻译： 公开了一种用于制造超高拉伸应力氮化物膜的方法。 首先执行PECVD处理以在衬底上沉积过渡氮化硅膜。 过渡氮化硅膜具有第一浓度的氢原子。 将过渡氮化硅膜进行UV固化，将氢原子的第一浓度降低至第二浓度的氢原子。

公开(公告)号：US06989337B2

公开(公告)日：2006-01-24

申请号：US10605478

申请日：2003-10-02

申请人： Hsiu-Chuan Chu ,  Chih-An Huang ,  Teng-Chun Tsai ,  Neng-Kuo Chen

发明人： Hsiu-Chuan Chu ,  Chih-An Huang ,  Teng-Chun Tsai ,  Neng-Kuo Chen

IPC分类号： H01L21/31

CPC分类号： H01L21/76224

摘要： A silicon oxide gap-filling process is described, wherein a CVD process having an etching effect is performed to fill up a trench with silicon oxide. The reaction gases used in the CVD process include deposition gases and He/H2 mixed gas as a sputtering-etching gas, wherein the percentage of the He/H2 mixed gas in the total reaction gases is raised with the increase of the aspect ratio of the trench.

摘要翻译： 描述了氧化硅间隙填充工艺，其中执行具有蚀刻效果的CVD工艺以用氧化硅填充沟槽。 在CVD工艺中使用的反应气体包括作为溅射蚀刻气体的沉积气体和He / H 2 H 2混合气体，其中He / H 2 H 2混合气体的百分比 在总反应中随着沟槽纵横比的增加气体的升高。

公开(公告)号：US06913978B1

公开(公告)日：2005-07-05

申请号：US10788183

申请日：2004-02-25

申请人： Neng-Kuo Chen ,  Hsiu-Chuan Chu ,  Chih-An Huang ,  Hsiao-Ling Lu ,  Teng-Chun Tsai

发明人： Neng-Kuo Chen ,  Hsiu-Chuan Chu ,  Chih-An Huang ,  Hsiao-Ling Lu ,  Teng-Chun Tsai

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L21/76235 ,  H01L21/76232

摘要： A method of fabricating a shallow trench isolation structure is disclosed. On a substrate, a pad oxide layer and a mask layer are successively formed. The pad oxide layer, the mask layer and a portion of the substrate are patterned to form a trench. After performing a rapid wet thermal process, a liner layer is formed on the exposed surface of the substrate, including the exposed silicon surface of the substrate in the trench and sidewalls and the surface of the mask layer. An oxide layer is deposited over the trench and the substrate and fills the trench. A planarization process is performed until the mask layer is exposed. The mask layer and the pad oxide layer are removed to complete the shallow trench isolation structure.

摘要翻译： 公开了一种制造浅沟槽隔离结构的方法。 在衬底上，依次形成衬垫氧化物层和掩模层。 衬垫氧化物层，掩模层和衬底的一部分被图案化以形成沟槽。 在进行快速湿热处理之后，在衬底的暴露表面上形成衬垫层，包括在沟槽中的衬底的暴露的硅表面以及掩模层的侧壁和表面。 在沟槽和衬底上沉积氧化物层并填充沟槽。 进行平坦化处理，直到掩模层被曝光。 去除掩模层和焊盘氧化物层以完成浅沟槽隔离结构。

公开(公告)号：US20130043512A1

公开(公告)日：2013-02-21

申请号：US13212834

申请日：2011-08-18

申请人： Gin-Chen Huang ,  Tsai-Fu Hsiao ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Hongfa Luan ,  Sey-Ping Sun ,  Clement Hsingjen Wann

发明人： Gin-Chen Huang ,  Tsai-Fu Hsiao ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Hongfa Luan ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC分类号： H01L21/31 ,  H01L21/28 ,  H01L29/78

CPC分类号： H01L21/02274 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02332 ,  H01L21/324 ,  H01L29/66795

摘要： Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.

公开(公告)号：US08367534B2

公开(公告)日：2013-02-05

申请号：US12884500

申请日：2010-09-17

申请人： Neng-Kuo Chen ,  Jeff J. Xu

发明人： Neng-Kuo Chen ,  Jeff J. Xu

IPC分类号： H01L21/20

CPC分类号： H01L21/02337 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/32115 ,  H01L21/32137

摘要： Provided is a method of planarizing a semiconductor device. The method includes providing a substrate. The method includes forming a first layer over the substrate. The method includes forming a second layer over the first layer. The first and second layers have different material compositions. The method includes forming a third layer over the second layer. The method includes performing a polishing process on the third layer until the third layer is substantially removed. The method includes performing an etch back process to remove the second layer and a portion of the first layer. Wherein an etching selectivity of the etch back process with respect to the first and second layers is approximately 1:1.

摘要翻译： 提供了一种使半导体器件平坦化的方法。 该方法包括提供基板。 该方法包括在衬底上形成第一层。 该方法包括在第一层上形成第二层。 第一层和第二层具有不同的材料组成。 该方法包括在第二层上形成第三层。 该方法包括在第三层上进行抛光处理，直到第三层基本上被去除。 该方法包括执行回蚀处理以去除第二层和第一层的一部分。 其中相对于第一层和第二层的蚀刻返回工艺的蚀刻选择性为约1:1。

公开(公告)号：US07846804B2

公开(公告)日：2010-12-07

申请号：US11758623

申请日：2007-06-05

申请人： Hsiu-Lien Liao ,  Neng-Kuo Chen ,  Teng-Chun Tsai ,  Yi-Wei Chen

发明人： Hsiu-Lien Liao ,  Neng-Kuo Chen ,  Teng-Chun Tsai ,  Yi-Wei Chen

IPC分类号： H01L21/336

CPC分类号： H01L21/324 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7843

摘要： A method and an apparatus for fabricating a high tensile stress film includes providing a substrate, forming a poly stressor on the substrate, and performing an ultra violet rapid thermal process (UVRTP) for curing the poly stressor and adjusting its tensile stress status, thus the poly stressor serves as a high tensile stress film. Due to a combination of energy from photons and heat, the tensile stress status of the high tensile stress film is adjusted in a relatively shorter process period or under a relatively lower temperature.

摘要翻译： 用于制造高拉伸应力膜的方法和装置包括提供基板，在基板上形成多应力器，并执行紫外线快速热处理（UVRTP），用于固化聚应力器并调整其拉伸应力状态，因此 多应力器作为高拉伸应力膜。 由于来自光子和热的能量的组合，高拉伸应力膜的拉伸应力状态在相对较短的工艺周期或相对较低的温度下调节。

公开(公告)号：US20090280614A1

公开(公告)日：2009-11-12

申请号：US12503042

申请日：2009-07-14

申请人： Neng-Kuo Chen ,  Chien-Chung Huang ,  Jei-Ming Chen

发明人： Neng-Kuo Chen ,  Chien-Chung Huang ,  Jei-Ming Chen

IPC分类号： H01L21/336

CPC分类号： H01L21/2652 ,  H01L21/2658 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A method is disclosed to make a strained-silicon PMOS or CMOS transistor, in which, a compressive stress film is formed by reacting a silane having at least one substituent selected from the group consisting of hydrocarbyl, hydrocarboxy, carbonyl, formyl, carboxylic group, ester group, and halo group and ammonia, or a conventional compressive stress film is implanted with fluorine atoms, oxygen atoms, or carbon atoms, so as to improve the properties of negative bias temperature instability (NBTI).

摘要翻译： 公开了制造应变硅PMOS或CMOS晶体管的方法，其中通过使具有至少一个选自烃基，烃羧基，羰基，甲酰基，羧基的取代基的硅烷反应形成压应力膜， 酯基，卤代基和氨，或者常规的压应力膜注入氟原子，氧原子或碳原子，以提高负偏压温度不稳定性（NBTI）的性质。

公开(公告)号：US20090274852A1

公开(公告)日：2009-11-05

申请号：US12496652

申请日：2009-07-02

申请人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang

发明人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang

IPC分类号： B05D1/00

CPC分类号： H01L21/31633 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/823807 ,  H01L23/3192 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating strained silicon transistors is disclosed. First, a semiconductor substrate is provided, in which the semiconductor substrate includes a gate, at least a spacer, and a source/drain region formed thereon. Next, a precursor, silane, and ammonia are injected, in which the precursor is reacted with silane and ammonia to form a high compressive stress film on the surface of the gate, the spacer, and the source/drain region. Preferably, the high compressive stress film can be utilized in the fabrication of a poly stressor, a contact etch stop layer, and dual contact etch stop layers.

摘要翻译： 公开了制造应变硅晶体管的方法。 首先，提供半导体衬底，其中半导体衬底包括栅极，至少一个间隔物和形成在其上的源极/漏极区域。 接下来，注入前体，硅烷和氨，其中前体与硅烷和氨反应，以在栅极，间隔物和源极/漏极区的表面上形成高压缩应力膜。 优选地，高压缩应力膜可以用于制造多应力器，接触蚀刻停止层和双接触蚀刻停止层。

公开(公告)号：US07585790B2

公开(公告)日：2009-09-08

申请号：US11459008

申请日：2006-07-20

申请人： Wen-Han Hung ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Chia-Wen Liang ,  Neng-Kuo Chen

发明人： Wen-Han Hung ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Chia-Wen Liang ,  Neng-Kuo Chen

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L29/7833 ,  H01L21/823807 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

摘要： A method of forming a semiconductor device. The method comprises steps of providing a substrate having a first transistor, a second transistor and non-salicide device formed thereon and the conductive type of the first transistor is different from that of the second transistor. A buffer layer is formed over the substrate and a tensile material layer is formed over the buffer layer. A portion of the tensile material layer over the second transistor is thinned and a spike annealing process is performed. The tensile material layer is removed to expose the buffer layer over the substrate and a patterned salicide blocking layer is formed over the non-salicide device. A salicide process is performed for forming a salicide layer on a portion of the first transistor and the second transistor.

摘要翻译： 一种形成半导体器件的方法。 该方法包括以下步骤：提供具有形成在其上的第一晶体管，第二晶体管和非自对准硅化物器件的衬底，并且第一晶体管的导电类型与第二晶体管的导电类型不同。 在衬底上形成缓冲层，并在缓冲层上形成拉伸材料层。 第二晶体管上的拉伸材料层的一部分变薄，并且执行尖峰退火处理。 除去拉伸材料层以暴露衬底上的缓冲层，并且在非自对准硅化物器件上形成图案化的自对准硅化物阻挡层。 执行自对准处理以在第一晶体管和第二晶体管的一部分上形成自对准硅化物层。