公开(公告)号：US06180501B2

公开(公告)日：2001-01-30

申请号：US09418036

申请日：1999-10-14

申请人： Kin-Leong Pey ,  Chaw Sing Ho ,  Lap Chan

发明人： Kin-Leong Pey ,  Chaw Sing Ho ,  Lap Chan

IPC分类号： H01L213205

CPC分类号： H01L29/6659 ,  H01L21/28035 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66545

摘要： This invention relates to the fabrication of integrated circuit devices and more particularly to a method for minimizing the localized mechanical stress problems that can occur when silicided polysilicon gates are used to fabricate narrow channel CMOS devices. The invention addresses the avoidance of typical stress-induced problems in polysilicon gates, such as non-uniform silicide (including bowing, thinning edges, etc.) and voids, which are becoming increasingly worse as gate lengths continue to be reduced. The key to this invention is to spread the highly detrimental mechanical stresses, in narrow silicided gates, over a larger vertical surface area. This is accomplished by using a thin/thick double polysilicon stack for the gate, whereby, the lower thin polysilicon gate layer is not silicided and the upper thick polysilicon layer is subsequently silicided. An insulating layer is used to prevent silicidation of the lower thin polysilicon gate, during silicidation of active source-drain regions. The same insulating layer is also used to avoid another cause of mechanical stress, by protecting the surface grain boundaries of the lower thin polysilicon gate layer from being stuffed with polymer during the dry etching used for spacer formation. The tall stacked gate structure allows the silicide-induced stresses to be more safely located farther away from the active devices.

摘要翻译： 本发明涉及集成电路器件的制造，更具体地说，涉及一种使硅化多晶硅栅极用于制造窄沟道CMOS器件时可能出现的局部机械应力问题最小化的方法。 本发明解决了避免多晶硅栅极中的典型的应力引起的问题，例如不均匀的硅化物（包括弯曲，变薄边缘等）和空隙，随着栅极长度的不断减小，这些问题变得越来越严重。 本发明的关键是在狭窄的硅化物栅极中，在较大的垂直表面积上传播高度有害的机械应力。 这是通过使用用于栅极的薄/厚双重多晶硅堆叠实现的，由此，下部薄多晶硅栅极层不被硅化，并且随后硅化上部厚多晶硅层。 在有源源极 - 漏极区域的硅化期间，使用绝缘层来防止下部薄多晶硅栅极的硅化。 同样的绝缘层也用于通过在用于间隔物形成的干蚀刻期间保护下部薄多晶硅栅极层的表面晶界不被聚合物填充而避免机械应力的另一个原因。 高堆叠栅极结构允许硅化物引起的应力更安全地远离有源器件。

公开(公告)号：US6143598A

公开(公告)日：2000-11-07

申请号：US246893

申请日：1999-02-08

申请人： John Elmslie Martin ,  Lap Chan ,  John Leonard Sudijono ,  Ting Cheong Ang

发明人： John Elmslie Martin ,  Lap Chan ,  John Leonard Sudijono ,  Ting Cheong Ang

IPC分类号： H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242

CPC分类号： H01L28/40 ,  H01L28/60 ,  H01L21/3144 ,  H01L21/31604 ,  H01L27/10852

摘要： A capacitor element of a semiconductor device used for high density semiconductor circuits is formed by the steps of forming the bottom plate of the capacitor, submitting the top of the bottom plate to plasma treatment in an oxidizing medium where nitrogen and oxygen are present, depositing a dielectric layer and submitting the top of the dielectric layer to plasma treatment in an oxidizing medium where nitrogen and oxygen are present. Various materials are used for the plasma treatment in an oxidizing medium where nitrogen and oxygen are present. While the present invention uses amorphous silicon as the dielectric material, plasma treatment in an oxidizing medium where nitrogen and oxygen are present can readily applied to a number of other dielectric materials. The objective in constructing capacitors for semiconductor circuits is to reduce the thickness of the dielectric material as much as possible and use a dielectric material for the dielectric which has a high dielectric constant, this increases the value of the capacitor electrical charge which can be carried by the capacitor. The objective of the present invention is to eliminate the leakage current between the plates of a capacitor so that the capacitor can maintain a high voltage between the top and the bottom plate.

摘要翻译： 用于高密度半导体电路的半导体器件的电容器元件是通过形成电容器的底板的步骤形成的，将底板的顶部在存在氮和氧的氧化介质中进行等离子体处理， 介电层，并将介电层的顶部在存在氮和氧的氧化介质中进行等离子体处理。 在存在氮和氧的氧化介质中使用各种材料进行等离子体处理。 虽然本发明使用非晶硅作为介电材料，但在存在氮和氧的氧化介质中的等离子体处理可以容易地应用于许多其它电介质材料。 用于半导体电路构造电容器的目的是尽可能地减小电介质材料的厚度，并且使用具有高介电常数的电介质的介电材料，这增加了电容器电荷的值 电容器。 本发明的目的是消除电容器板之间的漏电流，使得电容器能够在顶板和底板之间保持高电压。

公开(公告)号：US6140237A

公开(公告)日：2000-10-31

申请号：US294048

申请日：1999-04-19

申请人： Lap Chan ,  Jia Zhen Zheng

发明人： Lap Chan ,  Jia Zhen Zheng

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L21/76834 ,  H01L21/76843 ,  H01L23/53238 ,  H01L2924/0002

摘要： A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.

摘要翻译： 描述了在集成电路中制造铜互连的结构和方法。 该结构是镶嵌铜连接器，其上表面与嵌入其中的绝缘层的上表面共面。 通过两个阻挡层防止铜从连接器的扩散。 一个位于连接器和绝缘层之间的界面处，而第二屏障是覆盖连接器的上表面的绝缘层。 镶嵌工艺包括用铜填充绝缘体表面的沟槽，然后通过化学去除多余的沟槽。 抛光。 由于光致抗蚀剂从不与铜直接接触，因此已经有效地消除了抗蚀剂灰化期间铜氧化的问题。

公开(公告)号：US5948700A

公开(公告)日：1999-09-07

申请号：US650694

申请日：1996-05-20

申请人： Jia Zhen Zheng ,  Lap Chan

发明人： Jia Zhen Zheng ,  Lap Chan

IPC分类号： H01L21/3105 ,  H01L21/306

CPC分类号： H01L21/31053

摘要： A method of planarizing integrated circuit wafers using chemical mechanical polishing with an automatic end point and without using an etchback step. An electrode pattern is formed in a layer of soft metal, such as Al/Cu/Si, capped with a layer of hard metal such as tungsten. A layer of first oxide, a layer of spin on glass, and a layer of second oxide are formed over the electrode pattern. The layer of first oxide, the layer of spin on glass, and the layer of second oxide are then planarized using chemical mechanical polishing. The hard metal cap on the electrode pattern can not be removed by the chemical mechanical polishing and forms an automatic end point. The electric current powering the motor driving the chemical mechanical polishing changes when the hard metal cap is reached and this change can be used to detect the end point.

摘要翻译： 使用具有自动终点的化学机械抛光并且不使用回蚀步骤来平面化集成电路晶片的方法。 电极图案形成在诸如Al / Cu / Si的软金属层中，其被诸如钨的硬金属层覆盖。 在电极图案之上形成第一氧化物层，玻璃上的自旋层和第二氧化物层。 然后使用化学机械抛光使第一氧化物层，玻璃上的自旋层和第二氧化物层平坦化。 电极图案上的硬金属盖不能通过化学机械抛光去除并形成自动终点。 驱动化学机械抛光的电机的电流在达到硬金属帽时发生变化，并且可以使用该变化来检测终点。

公开(公告)号：US5900672A

公开(公告)日：1999-05-04

申请号：US876915

申请日：1997-06-16

申请人： Lap Chan ,  Jia Zhen Zheng

发明人： Lap Chan ,  Jia Zhen Zheng

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76834 ,  H01L21/76843 ,  H01L23/53238 ,  H01L2924/0002

摘要： A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.

摘要翻译： 描述了在集成电路中制造铜互连的结构和方法。 该结构是镶嵌铜连接器，其上表面与嵌入其中的绝缘层的上表面共面。 通过两个阻挡层防止铜从连接器的扩散。 一个位于连接器和绝缘层之间的界面处，而第二屏障是覆盖连接器的上表面的绝缘层。 镶嵌工艺包括用铜填充绝缘体表面的沟槽，然后通过化学去除多余的沟槽。 抛光。 由于光致抗蚀剂从不与铜直接接触，因此已经有效地消除了抗蚀剂灰化期间铜氧化的问题。

公开(公告)号：US5808855A

公开(公告)日：1998-09-15

申请号：US730009

申请日：1996-10-11

申请人： Lap Chan ,  Yeow Meng Teo

发明人： Lap Chan ,  Yeow Meng Teo

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L27/06 ,  H01L27/108 ,  H01G4/06

CPC分类号： H01L28/40 ,  H01L21/76895 ,  H01L27/0629 ,  H01L27/108 ,  H01L28/60 ,  H01L28/82 ,  H01L28/90

摘要： A method for forming a stacked container capacitor for use within integrated circuits. Formed successively upon a semiconductor substrate is a first dielectric layer, a second dielectric layer and a patterned mask layer. Within an isotropic etch process, the first dielectric layer etches slower than the second dielectric layer. By means of an anisotropic etch process employing the patterned mask layer as a mask, an aperture is etched at least partially through the first dielectric layer. By means of an isotropic etch process employing the patterned mask layer as a mask, the second dielectric layer is etched to yield a ledge formed above the first dielectric layer and below the patterned masking layer. The patterned mask layer is then removed. Formed then into the anisotropically and isotropically etched aperture is a first polysilicon layer, a third dielectric layer and a second polysilicon layer. Finally, the filled isotropically etched aperture is planarized until there is exposed a flange of the first polysilicon layer formed into the ledge.

摘要翻译： 一种用于形成集成电路内使用的层叠容器电容器的方法。 连续形成在半导体衬底上的是第一电介质层，第二电介质层和图案化掩模层。 在各向同性蚀刻工艺中，第一介电层比第二介电层慢。 通过使用图案化掩模层作为掩模的各向异性蚀刻工艺，至少部分地蚀刻孔，穿过第一介电层。 通过使用图案化掩模层作为掩模的各向同性蚀刻工艺，蚀刻第二介电层以产生形成在第一介电层上方并在图案化掩模层下方的凸缘。 然后去除图案化的掩模层。 然后形成各向异性和各向异性蚀刻的孔径是第一多晶硅层，第三介电层和第二多晶硅层。 最后，填充的各向同性蚀刻的孔被平坦化，直到暴露出形成在凸缘中的第一多晶硅层的凸缘。

公开(公告)号：US5792708A

公开(公告)日：1998-08-11

申请号：US611585

申请日：1996-03-06

申请人： Mei Sheng Zhou ,  Lap Chan ,  Young-Tong Tsai

发明人： Mei Sheng Zhou ,  Lap Chan ,  Young-Tong Tsai

IPC分类号： H01L21/3213 ,  H01L21/08

CPC分类号： H01L21/32137

摘要： A method for forming a residue free patterned polysilicon layer upon a high step height patterned substrate layer. First, there is provided a semiconductor substrate having formed thereon a high step height patterned substrate layer. Formed upon the high step height patterned substrate layer is a polysilicon layer, and formed upon the polysilicon layer is a patterned photoresist layer. The patterned photoresist layer exposes portions of the polysilicon layer at a lower step level of the high step height patterned substrate layer. The polysilicon layer is then patterned through the patterned photoresist layer as an etch mask employing an anisotropic first etch process to yield a patterned polysilicon layer upon the surface of the high step height patterned substrate layer and polysilicon residues at the lower step level of the high step height patterned substrate layer. The anisotropic first etch process is a Reactive Ion Etch (RIE) anisotropic first etch process which simultaneously passivates the exposed sidewall edges of the patterned polysilicon layer. Finally, the polysilicon residues formed at the lower step level of the high step height patterned substrate layer are removed through an isotropic second etch process. The isotropic second etch process is a Reactive Ion Etch (RIE) isotropic second etch process which employs hydrogen bromide (HBr) and sulfur hexafluoride (SF6) as the reactant gases.

摘要翻译： 一种用于在高台阶高度图案化衬底层上形成无残留图案化多晶硅层的方法。 首先，提供在其上形成有高台阶高度图案化基板层的半导体基板。 形成在高台阶高度图案化衬底层上的是多晶硅层，并且在多晶硅层上形成图案化的光致抗蚀剂层。 图案化的光致抗蚀剂层在高阶高度图案化衬底层的较低台阶处暴露多晶硅层的部分。 然后通过图案化的光致抗蚀剂层将多晶硅层图案化为使用各向异性第一蚀刻工艺的蚀刻掩模，以在高阶高度图案化衬底层的表面上产生图案化多晶硅层，并在高级步骤的较低级别处产生多晶硅残余物 高度图案化衬底层。 各向异性第一蚀刻工艺是反应离子蚀刻（RIE）各向异性第一蚀刻工艺，其同时钝化图案化多晶硅层的暴露的侧壁边缘。 最后，通过各向同性的第二蚀刻工艺去除在高阶高度图案化衬底层的较低台阶处形成的多晶硅残余物。 各向同性第二蚀刻工艺是使用溴化氢（HBr）和六氟化硫（SF6）作为反应气体的反应离子蚀刻（RIE）各向同性第二蚀刻工艺。

公开(公告)号：US5792672A

公开(公告)日：1998-08-11

申请号：US618891

申请日：1996-03-20

申请人： Lap Chan ,  Simon Chooi Yen Meng ,  Tony Chan

发明人： Lap Chan ,  Simon Chooi Yen Meng ,  Tony Chan

IPC分类号： G03F7/42 ,  H01L21/311 ,  H01L21/465

CPC分类号： H01L21/31138 ,  G03F7/427

摘要： An improved method for removing a photoresist mask from an etched aluminum pattern after etching the pattern in a chlorine containing plasma has been created. The method is a two step process, in which a first stripping step is in a plasma containing O.sub.2 and H.sub.2 O and a second stripping step is in a plasma containing O.sub.2.

摘要翻译： 已经产生了一种用于在含氯等离子体中蚀刻图案之后从蚀刻铝图案去除光致抗蚀剂掩模的改进方法。 该方法是两步法，其中第一汽提步骤在含有O 2和H 2 O的等离子体中，第二汽提步骤在含有O 2的等离子体中。

公开(公告)号：US5744376A

公开(公告)日：1998-04-28

申请号：US630709

申请日：1996-04-08

申请人： Lap Chan ,  Jia Zhen Zheng

发明人： Lap Chan ,  Jia Zhen Zheng

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/28

CPC分类号： H01L21/76834 ,  H01L21/76843 ,  H01L23/53238 ,  H01L2924/0002

摘要： A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer ,while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.

摘要翻译： 描述了在集成电路中制造铜互连的结构和方法。 该结构是镶嵌铜连接器，其上表面与嵌入其中的绝缘层的上表面共面。 通过两个阻挡层防止铜从连接器的扩散。 一个位于连接器和绝缘层之间的界面处，而第二屏障是覆盖连接器的上表面的绝缘层。 镶嵌工艺包括用铜填充绝缘体表面的沟槽，然后通过化学去除多余的沟槽。 抛光。 由于光致抗蚀剂从不与铜直接接触，因此已经有效地消除了抗蚀剂灰化期间铜氧化的问题。

公开(公告)号：US5610083A

公开(公告)日：1997-03-11

申请号：US650697

申请日：1996-05-20

申请人： Lap Chan ,  Ravis H. Sundaresan ,  Che-Chia Wei

发明人： Lap Chan ,  Ravis H. Sundaresan ,  Che-Chia Wei

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1203

摘要： A process for creating a back gate contact, in an SOI layer, that can easily be incorporated into a MOSFET fabrication recipe, has been developed. The back gate contact consists of a etched trench, lined with insulator, and filled with doped polysilicon. The polysilicon filled trench electrically connects the semiconductor substrate to overlying metal contacts.

摘要翻译： 已经开发了用于在SOI层中产生可以容易地并入MOSFET制造配方中的背栅极接触的工艺。 背栅极接触由蚀刻的沟槽组成，内衬绝缘体并填充有多晶硅。 多晶硅填充沟槽将半导体衬底电连接到覆盖的金属触点。