公开(公告)号：US07078259B2

公开(公告)日：2006-07-18

申请号：US10707746

申请日：2004-01-08

申请人： Jon A. Casey ,  William J. Ferrante ,  Edward W. Kiewra ,  Carl J. Radens ,  William R. Tonti

发明人： Jon A. Casey ,  William J. Ferrante ,  Edward W. Kiewra ,  Carl J. Radens ,  William R. Tonti

IPC分类号： H01L21/00

CPC分类号： H01L21/76895 ,  G01K7/226 ,  H01C7/006 ,  H01L21/76224 ,  H01L21/76838

摘要： A structure and method are provided for forming a thermistor. Isolation structures are formed in a substrate including at least an upper layer of a single crystal semiconductor. A layer of salicide precursor is deposited over the isolation region and the upper layer. The salicide precursor is then reacted with the upper layer to form a salicide self-aligned to the upper layer. Finally, the unreacted portions of the salicide precursor are then removed while preserving a portion of the salicide precursor over the isolation region as a body of the thermistor. An alternative integrated circuit thermistor is formed from a region of thermistor material in an embossed region of an interlevel dielectric (ILD).

摘要翻译： 提供了用于形成热敏电阻的结构和方法。 隔离结构形成在至少包括单晶半导体的上层的基板中。 一层自杀化合物前体沉积在隔离区和上层上。 然后将自对准硅化物前体与上层反应以形成与上层自对准的自对准硅化物。 最后，除去自对准硅胶前体的未反应部分，同时在作为热敏电阻体的隔离区域上保留一部分自杀化合物前体。 一种替代的集成电路热敏电阻由层间电介质（ILD）的压花区域中的热敏电阻材料的区域形成。

公开(公告)号：US07015552B2

公开(公告)日：2006-03-21

申请号：US11098103

申请日：2005-04-04

申请人： Qiuyi Ye ,  William R. Tonti ,  Yujun Li

发明人： Qiuyi Ye ,  William R. Tonti ,  Yujun Li

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/10888 ,  H01L21/76897 ,  H01L27/10894

摘要： A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.

公开(公告)号：US06621324B2

公开(公告)日：2003-09-16

申请号：US09683808

申请日：2002-02-19

申请人： John A. Fifield ,  William R. Tonti

发明人： John A. Fifield ,  William R. Tonti

IPC分类号： H01H3776

CPC分类号： H01L23/5252 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse structure for improved programming efficiency is disclosed wherein the antifuse structure including a first node providing a first voltage, a plurality of antifuse elements, and a plurality of first switches. The plurality of antifuse elements are commonly connected to the first node. The plurality of first switches are sequentially activated during a program mode to individually apply the first voltage to each antifuse element. The antifuse structure may include a second node to which a second voltage is provided. Each of the plurality of first switches may be coupled between the second node and a corresponding one of the plurality of antifuse elements. The antifuse structure may also include a third node to which a fuse latch is connected. A plurality of second switches may be coupled between the third node and a corresponding one of the plurality antifuse elements. The plurality of second switches may be simultaneously activated during a read mode.

摘要翻译： 公开了一种用于提高编程效率的反熔丝结构，其中反熔丝结构包括提供第一电压的第一节点，多个反熔丝元件和多个第一开关。 多个反熔丝元件通常连接到第一节点。 多个第一开关在编程模式期间被依次启动，以分别对每个反熔丝元件施加第一电压。 反熔丝结构可以包括提供第二电压的第二节点。 多个第一开关中的每一个可以耦合在第二节点和多个反熔丝元件中的对应的一个之间。 反熔丝结构还可以包括连接熔丝闩锁的第三节点。 多个第二开关可以耦合在第三节点和多个反熔丝元件中的对应的一个之间。 多个第二开关可以在读取模式期间同时被激活。

公开(公告)号：US06570207B2

公开(公告)日：2003-05-27

申请号：US09736496

申请日：2000-12-13

申请人： Louis L. Hsu ,  Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti

发明人： Louis L. Hsu ,  Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti

IPC分类号： H01L27108

CPC分类号： H01L27/10897 ,  H01L23/5252 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit chip is provided having both a conventional DRAM vertical transfer device and an integrated vertical storage capacitor or anti-fuse that can be accessed directly without having to turn on a transfer gate. The mechanism for accessing the integrated capacitor or anti-fuse directly can be a modified doping profile within the vertical cell that provides a low resistance punch-through FET. Alternatively, the mechanism can be a pair of overlapping or nearly overlapping diffusions within the vertical cell.

摘要翻译： 提供一种集成电路芯片，其具有常规DRAM垂直传送装置和可以直接访问的集成垂直存储电容器或反熔丝，而不必打开传输门。 直接访问集成电容器或反熔丝的机构可以是垂直单元内的修改的掺杂分布，其提供低电阻穿通FET。 或者，机构可以是垂直单元内的一对重叠或几乎重叠的扩散。

公开(公告)号：US06555891B1

公开(公告)日：2003-04-29

申请号：US09690674

申请日：2000-10-17

申请人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

发明人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

IPC分类号： H01L2900

CPC分类号： H01L27/10894 ,  H01L21/76262 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1207

摘要： A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.

公开(公告)号：US06538295B1

公开(公告)日：2003-03-25

申请号：US09645499

申请日：2000-08-25

申请人： Gary B. Bronner ,  Jeffrey P. Gambino ,  Louis L. Hsu ,  Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti

发明人： Gary B. Bronner ,  Jeffrey P. Gambino ,  Louis L. Hsu ,  Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti

IPC分类号： H01L2976

CPC分类号： H01L21/76897 ,  H01L27/10873 ,  H01L29/665

摘要： A method and structure for a field effect transistor structure for dynamic random access memory integrated circuit devices has a gate conductor, salicide regions positioned along sides of the gate conductor, a gate cap positioned above the gate conductor and at least one self-aligned contact adjacent the gate conductor.

摘要翻译： 用于动态随机存取存储器集成电路器件的场效应晶体管结构的方法和结构具有栅极导体，沿着栅极导体的侧面定位的自对准硅化物区域，位于栅极导体上方的栅极帽和邻近的至少一个自对准接触 门导体。

公开(公告)号：US06420749B1

公开(公告)日：2002-07-16

申请号：US09602427

申请日：2000-06-23

申请人： Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Edward W. Kiewra ,  Jack A. Mandelman ,  Carl Radens ,  William R. Tonti

发明人： Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Edward W. Kiewra ,  Jack A. Mandelman ,  Carl Radens ,  William R. Tonti

IPC分类号： H01L27108

CPC分类号： H01L21/823481 ,  H01L21/743 ,  H01L21/76232 ,  H01L21/76895 ,  H01L21/823475 ,  H01L27/10897

摘要： A method and structure for a semiconductor device which includes a substrate comprising trenches, a plurality of devices on the substrate isolated by the trenches, conductive sidewall spacers within the trenches, and an insulator filling the trenches between the conductive sidewall spacers. A first conductive sidewall spacer is electrically connected to a first device of said plurality of devices and a second conductive sidewall spacer is electrically connected to a second device of the plurality of devices. The first device can be biased independently of the second device. A contact extends above a surface of the substrate. A first contact abuts a first device and a first conductive sidewall spacer. An insulator separates the conductive sidewall spacers. A first contact may be equidistant between the first conductor and the second conductor. The conductive sidewall spacers comprise field shields.

摘要翻译： 一种用于半导体器件的方法和结构，其包括：衬底，其包括沟槽，在衬底上隔离的衬底上的多个器件，沟槽内的导电侧壁间隔物，以及填充导电侧壁间隔物之间​​的沟槽的绝缘体。 第一导电侧壁间隔件电连接到所述多个器件中的第一器件，并且第二导电侧壁间隔件电连接到多个器件中的第二器件。 第一装置可以独立于第二装置而被偏置。 接触件在衬底的表面上方延伸。 第一接触件邻接第一器件和第一导电侧壁间隔物。 绝缘体将导电侧墙隔离开。 第一接触件可以在第一导体和第二导体之间等距。 导电侧壁间隔件包括场屏蔽。

公开(公告)号：US06380027B2

公开(公告)日：2002-04-30

申请号：US09225127

申请日：1999-01-04

申请人： Toshiharu Furukawa ,  Jeffrey P. Gambino ,  Edward W. Kiewra ,  Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti ,  Mary E. Weybright

发明人： Toshiharu Furukawa ,  Jeffrey P. Gambino ,  Edward W. Kiewra ,  Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti ,  Mary E. Weybright

IPC分类号： H01L21242

CPC分类号： H01L27/10876 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10894

摘要： A structure and method for simultaneously forming array structures and support structures on a substrate comprises forming the array structures to have a V-groove, forming the support structures to have a planar surface, and simultaneously forming a first oxide in the V-groove and a second oxide in the planar surface, wherein the first oxide is thicker than the second oxide.

摘要翻译： 用于在衬底上同时形成阵列结构和支撑结构的结构和方法包括：形成阵列结构以具有V形槽，形成支撑结构以具有平坦表面，同时在V形槽中形成第一氧化物，以及 其中所述第一氧化物比所述第二氧化物厚。

公开(公告)号：US06274441B1

公开(公告)日：2001-08-14

申请号：US09560073

申请日：2000-04-27

申请人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  William R. Tonti

发明人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  William R. Tonti

IPC分类号： H01L2170

CPC分类号： H01L29/1045 ,  H01L21/266 ,  H01L27/10861 ,  H01L27/10873 ,  H01L27/10888 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66659

摘要： A method for fabricating a MOSFET device including a halo implant comprising providing a semiconductor substrate, a gate insulator layer, a conductor layer, an overlying silicide layer, and an insulating cap; patterning and etching the silicide layer and the insulating cap; providing insulating spacers along sides of said silicide layer and insulating cap; implanting node and bitline N+ diffusion regions; patterning a photoresist layer to protect the node diffusion region and supporting PFET source and drain regions and expose the bitline diffusion region and NFET source and drain regions; etching exposed spacer material from the side of said silicide layer and insulating cap; implanting a P-type impurity halo implant into the exposed bitline diffusion region and supporting NFET source and drain regions; and stripping the photoresist layer and providing an insulating spacer along the exposed side of said silicide layer and insulating cap.

摘要翻译： 一种制造包括卤素注入的MOSFET器件的方法，包括提供半导体衬底，栅极绝缘体层，导体层，上覆硅化物层和绝缘帽; 图案化和蚀刻硅化物层和绝缘帽; 在所述硅化物层和绝缘盖的侧面提供绝缘垫片; 植入节点和位线N +扩散区域; 图案化光致抗蚀剂层以保护节点扩散区域并支持PFET源极和漏极区域并暴露位线扩散区域和NFET源极和漏极区域; 从所述硅化物层和绝缘盖的侧面蚀刻暴露的间隔物材料; 将P型杂质卤素注入植入暴露的位线扩散区并支持NFET源极和漏极区; 并剥离光致抗蚀剂层，并沿着所述硅化物层和绝缘帽的暴露侧提供绝缘间隔物。

公开(公告)号：US06222276B1

公开(公告)日：2001-04-24

申请号：US09056277

申请日：1998-04-07

申请人： Claude Louis Bertin ,  Wayne John Howell ,  William R. Tonti ,  Jerzy Maria Zalesinski

发明人： Claude Louis Bertin ,  Wayne John Howell ,  William R. Tonti ,  Jerzy Maria Zalesinski

IPC分类号： H01L2352

CPC分类号： H01L23/13 ,  H01L23/3677 ,  H01L23/481 ,  H01L2223/6622 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2924/19104 ,  H01L2924/00014

摘要： Through-chip conductors for low inductance chip-to-chip integration and off-chip connections in a semiconductor package is disclosed. A semiconductor device has active devices on the front surface, a first through-chip conductor having first electrical/physical characteristics passing from the front surface of the device to the back surface, a second through-chip conductor having second electrical/physical characteristics passing to the back surface, and an off-chip or chip-to-chip connector electrically connecting the active devices on the front surface to a different level of packaging.